Re: [PATCH 3/9] oprofile, perf, x86: introduce new functions to reserve perfctrs by index

[Robert Richter <robert.richter@amd.com>]

Andi,

so far it does not seem this reservation patches will go upstream. So
we still do not have a solution of how to share the pmu with perf. The
current approach is a global pmu lock. I don't think this is a good
solution and we already see questions on the oprofile mailing list why
counters are not available to use. This will become much worse if perf
is using counters permanently in the kernel (e.g. the perf nmi
watchdog). This will make oprofile unusable.

On 20.03.10 06:45:44, Andi Kleen wrote:
> Robert Richter <robert.richter@amd.com> writes:
> 
> > Current perfctr reservation code allocates single pmu msrs. The msr
> > addresses may differ depending on the model and offset calculation is
> > necessary. This can be easier implemented by reserving a counter by
> > its index only.
> 
> Sorry reviewing old patch. This doesn't work for the fixed counters on intel,
> which don't have a index (or rather they have a separate number space)
> 
> I had a old patch to fix the reservation for them (and a matching
> patch to perf to use it).
> 
> How to resolve this?

Fixed counter reservation is not really used in the kernel except for
p4. Oprofile only reserves generic counters. Unless there is a general
solution how to reserve counters I don't see the need to extend the
reservation code for fixed counters since the only subsystem using it
would be the nmi watchdog.

-Robert

-- 
Advanced Micro Devices, Inc.
Operating System Research Center
email: robert.richter@amd.com