From: Borislav Petkov <bp@amd64.org>
To: "H. Peter Anvin" <hpa@zytor.com>
Cc: mingo@elte.hu, tglx@linutronix.de, x86@kernel.org,
linux-kernel@vger.kernel.org, Frank Arnold <frank.arnold@amd.com>
Subject: Re: [PATCH 4/5] x86, cacheinfo: Make L3 cache info per node
Date: Wed, 21 Apr 2010 23:05:34 +0200 [thread overview]
Message-ID: <20100421210534.GA31028@aftab> (raw)
In-Reply-To: <4BCF6425.7040908@zytor.com>
From: "H. Peter Anvin" <hpa@zytor.com>
Date: Wed, Apr 21, 2010 at 01:46:29PM -0700
> On 04/15/2010 09:41 AM, Borislav Petkov wrote:
> > +
> > +/* max 8 nodes on a system */
> > +static struct amd_l3_cache * __cpuinitdata l3_caches[8];
> > +
>
> This makes me very nervous. Where does this limit come from? It
> appears completely arbitrary and seems like begging for problems in the
> future.
Right. So, we currently have a 3-bit field for the node id of each node,
in conjunction with the L3 cache this means one L3 cache per node. It is
located in F0x60[2:0]. This field is setup to the proper value by the
BIOS.
But yeah, I see your point. I could try initializing it dynamically
per system so that there are no out of bounds accesses. Let me cook up
something tomorrow.
--
Regards/Gruss,
Boris.
--
Advanced Micro Devices, Inc.
Operating Systems Research Center
next prev parent reply other threads:[~2010-04-21 21:05 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-04-15 16:40 [PATCH 0/5] AMD L3 cache index disable fixes for .35 Borislav Petkov
2010-04-15 16:40 ` [PATCH 1/5] x86, cacheinfo: Unify AMD L3 cache index disable checking Borislav Petkov
2010-04-15 16:41 ` [PATCH 2/5] x86, cacheinfo: Turn off L3 cache index disable feature in virtualized environments Borislav Petkov
2010-04-15 16:41 ` [PATCH 3/5] x86, cacheinfo: Reorganize AMD L3 cache structure Borislav Petkov
2010-04-15 16:41 ` [PATCH 4/5] x86, cacheinfo: Make L3 cache info per node Borislav Petkov
2010-04-21 20:46 ` H. Peter Anvin
2010-04-21 21:05 ` Borislav Petkov [this message]
2010-04-15 16:41 ` [PATCH 5/5] x86, cacheinfo: Disable index in all four subcaches Borislav Petkov
2010-04-21 20:43 ` [PATCH 0/5] AMD L3 cache index disable fixes for .35 Borislav Petkov
-- strict thread matches above, loose matches on Subject: below --
2010-04-22 14:06 [PATCH -v2 " Borislav Petkov
2010-04-22 14:07 ` [PATCH 4/5] x86, cacheinfo: Make L3 cache info per node Borislav Petkov
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20100421210534.GA31028@aftab \
--to=bp@amd64.org \
--cc=frank.arnold@amd.com \
--cc=hpa@zytor.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mingo@elte.hu \
--cc=tglx@linutronix.de \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox