Re: Performance Events hangs with Intel P4 system

Jaswinder Singh Rajput
2010-05-14T16:36:50Z

Hello Cyrill,

On Fri, May 14, 2010 at 9:58 PM, Cyrill Gorcunov <gorcunov@gmail.com> wrote:
> On Fri, May 14, 2010 at 09:52:28PM +0530, Jaswinder Singh Rajput wrote:
> ...
>> Yes, this works for me. Now I am not getting general protection fault.
>>
>> It seems hardware events are not supported for P4 yet.
>>
>> $ ./perf stat -e
>> cycles,instructions,cache-references,cache-misses,branches,branch-misses,bus-cycles
>> ls > /dev/null
>>
>>  Performance counter stats for 'ls':
>>
>>   <not counted>  cycles
>>          601636  instructions             #      0.000 IPC    (scaled
>> from 91.80%)
>>   <not counted>  cache-references
>>   <not counted>  cache-misses
>>   <not counted>  branches
>>   <not counted>  branch-misses
>>   <not counted>  bus-cycles
>>
>>     0.003364910  seconds time elapsed
>
> Thanks Jaswinder,
>
> it means counters management somehow screwed at moment (it was working before).
> I'm working on it.
>

Ok, I added few more events and now I am able see few hardware events :

$ ./perf stat -e
cycles,instructions,cache-references,cache-misses,branches,branch-misses,bus-cycles,L1-dcache-loads,L1-dcache-load-misses,L1-dcache-stores,L1-dcache-store-misses,L1-dcache-prefetches,L1-dcache-prefetch-misses,L1-icache-loads,L1-icache-load-misses,L1-icache-prefetches,L1-icache-prefetch-misses,LLC-loads,LLC-load-misses,LLC-stores,LLC-store-misses,LLC-prefetches,LLC-prefetch-misses,dTLB-loads,dTLB-load-misses,dTLB-stores,dTLB-store-misses,dTLB-prefetches,dTLB-prefetch-misses,iTLB-loads,iTLB-load-misses
ls -lR /dev > /dev/null

Performance counter stats for 'ls -lR /dev':

<not counted> cycles
10159428 instructions # 0.000 IPC (scaled
from 11.71%)
<not counted> cache-references
<not counted> cache-misses
2160905 branches (scaled from 9.71%)
80630 branch-misses # 3.731 % (scaled
from 15.68%)
<not counted> bus-cycles
<not counted> L1-dcache-loads
90289 L1-dcache-load-misses (scaled from 14.23%)
<not counted> L1-dcache-stores
<not counted> L1-dcache-store-misses
<not counted> L1-dcache-prefetches
<not counted> L1-dcache-prefetch-misses
<not counted> L1-icache-loads
<not counted> L1-icache-load-misses
<not counted> L1-icache-prefetches
<not counted> L1-icache-prefetch-misses
<not counted> LLC-loads
3162 LLC-load-misses (scaled from 12.40%)
<not counted> LLC-stores
<not counted> LLC-store-misses
<not counted> LLC-prefetches
<not counted> LLC-prefetch-misses
<not counted> dTLB-loads
21825 dTLB-load-misses (scaled from 11.04%)
<not counted> dTLB-stores
1386 dTLB-store-misses (scaled from 9.96%)
<not counted> dTLB-prefetches
<not counted> dTLB-prefetch-misses
<not counted> iTLB-loads
<not counted> iTLB-load-misses

0.019403422 seconds time elapsed

Thanks, good work :-)

--
Jaswinder Singh.