From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752731Ab0EQQH6 (ORCPT ); Mon, 17 May 2010 12:07:58 -0400 Received: from mga07.intel.com ([143.182.124.22]:63974 "EHLO azsmga101.ch.intel.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752298Ab0EQQH5 (ORCPT ); Mon, 17 May 2010 12:07:57 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.53,248,1272870000"; d="scan'208";a="278010271" Date: Mon, 17 May 2010 09:07:55 -0700 From: jacob pan To: Thomas Gleixner Cc: LKML , "H. Peter Anvin" , Ingo Molnar , Alan Cox , Arjan van de Ven Subject: Re: [PATCH 2/8] x86/mrst: add cpu type detection for Medfield Message-ID: <20100517090755.000026d4@unknown> In-Reply-To: References: <1273873281-17489-1-git-send-email-jacob.jun.pan@linux.intel.com> <1273873281-17489-3-git-send-email-jacob.jun.pan@linux.intel.com> Organization: Intel OTC X-Mailer: Claws Mail 3.7.4cvs1 (GTK+ 2.16.0; i586-pc-mingw32msvc) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > >Why are you having mrst_cpu_chip as a caching variable if you expose >the identify function ? Either you evaluate boot_cpu_data everytime or >you do it once and expose a function which lets you access the cached >data. IIRC Alan mentioned that drivers need this info, so the access >function will need an EXPORT_SYMBOL_GPL to work. > I cached value because mrst_cpu_chip is used a few times in mrst.c, I should fix that to have a unified interface. will also do the EXPORT_SYMBOL_GPL. thanks.