[PATCH 0/8] v2 Moorestown core patches for 35 merge window

[PATCH 0/8] v2 Moorestown core patches for 35 merge window

[Jacob Pan]

Hi hpa, ingo, and tglx,

We have received many comments in v1, specifically regarding the consolidation
of timer calibration and frequency detection. These two items are being worked
on and require more time for restructuring. Therefore, i have separated them
out of the patch series. This series below only inlcude the parts that have
comments been addressed.

thanks,

Jacob

*** BLURB HERE ***

Feng Tang (2):
  x86/platform: add a wallclock_init func to x86_platforms ops
  x86/mrst: add vrtc driver which serves as a wall clock device

Jacob Pan (6):
  x86/mrst/pci: return 0 for non-present pci bars
  x86/mrst: add cpu type detection for Medfield
  x86/mrst: add more timer options to include Medfield
  x86/apbt: support more timer configurations on mrst
  x86/mrst: add nop functions to x86_init mpparse functions
  input: do not select i8042 for x86 mid

 arch/x86/include/asm/apb_timer.h |    2 +-
 arch/x86/include/asm/fixmap.h    |    4 ++
 arch/x86/include/asm/mrst.h      |   20 ++++++++
 arch/x86/include/asm/vrtc.h      |   27 ++++++++++
 arch/x86/include/asm/x86_init.h  |    2 +
 arch/x86/kernel/Makefile         |    2 +-
 arch/x86/kernel/apb_timer.c      |   18 ++++---
 arch/x86/kernel/mrst.c           |   97 +++++++++++++++++++++++++++++++++---
 arch/x86/kernel/setup.c          |    2 +
 arch/x86/kernel/vrtc.c           |  100 ++++++++++++++++++++++++++++++++++++++
 arch/x86/kernel/x86_init.c       |    2 +
 arch/x86/pci/mrst.c              |    2 +-
 drivers/input/keyboard/Kconfig   |    2 +-
 drivers/input/mouse/Kconfig      |    2 +-
 14 files changed, 260 insertions(+), 22 deletions(-)
 create mode 100644 arch/x86/include/asm/vrtc.h
 create mode 100644 arch/x86/kernel/vrtc.c

[PATCH 1/8] x86/mrst/pci: return 0 for non-present pci bars

[Jacob Pan]

Moorestown PCI code has special handling of devices with fixed BARs. In
case of BAR sizing writes, we need to update the fake PCI MMCFG space with real
size decode value.

When a BAR is not present, we need to return 0 instead of ~0. ~0 will be
treated as device error per bugzilla 12006.

Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 arch/x86/pci/mrst.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/x86/pci/mrst.c b/arch/x86/pci/mrst.c
index 8bf2fcb..d5c7aef 100644
--- a/arch/x86/pci/mrst.c
+++ b/arch/x86/pci/mrst.c
@@ -109,7 +109,7 @@ static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn,
 			decode++;
 			decode = ~(decode - 1);
 		} else {
-			decode = ~0;
+			decode = 0;
 		}
 
 		/*
-- 
1.6.3.3

Re: [PATCH 1/8] x86/mrst/pci: return 0 for non-present pci bars

[Thomas Gleixner]

On Fri, 14 May 2010, Jacob Pan wrote:

> Moorestown PCI code has special handling of devices with fixed BARs. In
> case of BAR sizing writes, we need to update the fake PCI MMCFG space with real
> size decode value.
> 
> When a BAR is not present, we need to return 0 instead of ~0. ~0 will be
> treated as device error per bugzilla 12006.
> 
> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Acked-by: Thomas Gleixner <tglx@linutronix.de>

> ---
>  arch/x86/pci/mrst.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/x86/pci/mrst.c b/arch/x86/pci/mrst.c
> index 8bf2fcb..d5c7aef 100644
> --- a/arch/x86/pci/mrst.c
> +++ b/arch/x86/pci/mrst.c
> @@ -109,7 +109,7 @@ static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn,
>  			decode++;
>  			decode = ~(decode - 1);
>  		} else {
> -			decode = ~0;
> +			decode = 0;
>  		}
>  
>  		/*
> -- 
> 1.6.3.3
> 

[tip:x86/mrst] x86, mrst, pci: return 0 for non-present pci bars

[tip-bot for Jacob Pan]

Commit-ID:  e4af4268a34d8cd28c46a03161fc017cbd2db887
Gitweb:     http://git.kernel.org/tip/e4af4268a34d8cd28c46a03161fc017cbd2db887
Author:     Jacob Pan <jacob.jun.pan@linux.intel.com>
AuthorDate: Fri, 14 May 2010 14:41:14 -0700
Committer:  H. Peter Anvin <hpa@linux.intel.com>
CommitDate: Sun, 16 May 2010 22:45:36 -0700

x86, mrst, pci: return 0 for non-present pci bars

Moorestown PCI code has special handling of devices with fixed BARs. In
case of BAR sizing writes, we need to update the fake PCI MMCFG space with real
size decode value.

When a BAR is not present, we need to return 0 instead of ~0. ~0 will be
treated as device error per bugzilla 12006.

Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
LKML-Reference: <1273873281-17489-2-git-send-email-jacob.jun.pan@linux.intel.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
---
 arch/x86/pci/mrst.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/x86/pci/mrst.c b/arch/x86/pci/mrst.c
index 8bf2fcb..d5c7aef 100644
--- a/arch/x86/pci/mrst.c
+++ b/arch/x86/pci/mrst.c
@@ -109,7 +109,7 @@ static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn,
 			decode++;
 			decode = ~(decode - 1);
 		} else {
-			decode = ~0;
+			decode = 0;
 		}
 
 		/*

Re: [PATCH 1/8] x86/mrst/pci: return 0 for non-present pci bars

[Bjorn Helgaas]

On Friday, May 14, 2010 03:41:14 pm Jacob Pan wrote:
> Moorestown PCI code has special handling of devices with fixed BARs. In
> case of BAR sizing writes, we need to update the fake PCI MMCFG space with real
> size decode value.
> 
> When a BAR is not present, we need to return 0 instead of ~0. ~0 will be
> treated as device error per bugzilla 12006.

It would be more convenient if you included the URL,
https://bugzilla.kernel.org/show_bug.cgi?id=12006,
rather than just the bugzilla number.

You probably noticed already, but we reverted the patch I
proposed in 12006 because it was too aggressive, so you may
not need this patch for that reason.

Per 6.2.5.1 in the PCI 3.0 spec, "unimplemented Base Address
registers are hardwired to zero," so it would make sense to me
to follow that, but your patch affects the *write* path, not
the read path, so I don't know how it's related to what
__pci_read_base() will see when it reads the BAR.

Bjorn

> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  arch/x86/pci/mrst.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/x86/pci/mrst.c b/arch/x86/pci/mrst.c
> index 8bf2fcb..d5c7aef 100644
> --- a/arch/x86/pci/mrst.c
> +++ b/arch/x86/pci/mrst.c
> @@ -109,7 +109,7 @@ static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn,
>  			decode++;
>  			decode = ~(decode - 1);
>  		} else {
> -			decode = ~0;
> +			decode = 0;
>  		}
>  
>  		/*
> 

Re: [PATCH 1/8] x86/mrst/pci: return 0 for non-present pci bars

[H. Peter Anvin]

On 05/17/2010 09:58 AM, Bjorn Helgaas wrote:
> On Friday, May 14, 2010 03:41:14 pm Jacob Pan wrote:
>> Moorestown PCI code has special handling of devices with fixed BARs. In
>> case of BAR sizing writes, we need to update the fake PCI MMCFG space with real
>> size decode value.
>>
>> When a BAR is not present, we need to return 0 instead of ~0. ~0 will be
>> treated as device error per bugzilla 12006.
> 
> It would be more convenient if you included the URL,
> https://bugzilla.kernel.org/show_bug.cgi?id=12006,
> rather than just the bugzilla number.
> 
> You probably noticed already, but we reverted the patch I
> proposed in 12006 because it was too aggressive, so you may
> not need this patch for that reason.
> 
> Per 6.2.5.1 in the PCI 3.0 spec, "unimplemented Base Address
> registers are hardwired to zero," so it would make sense to me
> to follow that, but your patch affects the *write* path, not
> the read path, so I don't know how it's related to what
> __pci_read_base() will see when it reads the BAR.
> 

Very simple... these device headers are really just data structures in
RAM, so what is written is what is read.

	-hpa

-- 
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel.  I don't speak on their behalf.

[PATCH 2/8] x86/mrst: add cpu type detection for Medfield

[Jacob Pan]

Medfield is the follow-up of Moorestown, it is treated under the same
HW sub-architecture. However, we do need to know the CPU type such that
some drivers can act accordingly.

We also have different optimal clock configuration for each CPU type.
For Moorestown the CPU type is Lincroft and for Medfield the CPU type is
Penwell.

Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
---
 arch/x86/include/asm/mrst.h |   13 +++++++++++++
 arch/x86/kernel/mrst.c      |   21 +++++++++++++++++++++
 2 files changed, 34 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/mrst.h b/arch/x86/include/asm/mrst.h
index 451d30e..ddf0ad8 100644
--- a/arch/x86/include/asm/mrst.h
+++ b/arch/x86/include/asm/mrst.h
@@ -11,8 +11,21 @@
 #ifndef _ASM_X86_MRST_H
 #define _ASM_X86_MRST_H
 extern int pci_mrst_init(void);
+extern int mrst_identify_cpu(void);
 int __init sfi_parse_mrtc(struct sfi_table_header *table);
 
+/**
+ * Medfield is the follow-up of Moorestown, it combines two chip solution into
+ * one. Other than that it also added always-on and constant tsc and lapic
+ * timers. Medfield is the platform name, and the chip name is called Penwell
+ * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
+ * identified via MSRs.
+ */
+enum mrst_cpu_type {
+	MRST_CPU_CHIP_LINCROFT = 1,
+	MRST_CPU_CHIP_PENWELL,
+};
+
 #define SFI_MTMR_MAX_NUM 8
 #define SFI_MRTC_MAX	8
 
diff --git a/arch/x86/kernel/mrst.c b/arch/x86/kernel/mrst.c
index 0aad867..a3e85be 100644
--- a/arch/x86/kernel/mrst.c
+++ b/arch/x86/kernel/mrst.c
@@ -27,6 +27,7 @@
 
 static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
 static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
+static u32 mrst_cpu_chip;
 int sfi_mtimer_num;
 
 struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
@@ -216,6 +217,26 @@ static void __init mrst_setup_boot_clock(void)
 		setup_boot_APIC_clock();
 };
 
+int mrst_identify_cpu(void)
+{
+	if (boot_cpu_data.x86 == 6 &&
+		boot_cpu_data.x86_model == 0x27 &&
+		boot_cpu_data.x86_mask == 1)
+		mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;
+	else if (boot_cpu_data.x86 == 6 &&
+		boot_cpu_data.x86_model == 0x26)
+		mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
+	else {
+		pr_err("Unknown Moorestown CPU type, default to Lincroft\n");
+		mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
+	}
+	pr_debug("Moorestown CPU %s identified\n",
+		(mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) ?
+		"Lincroft" : "Penwell");
+
+	return mrst_cpu_chip;
+}
+
 /*
  * Moorestown specific x86_init function overrides and early setup
  * calls.
-- 
1.6.3.3

Re: [PATCH 2/8] x86/mrst: add cpu type detection for Medfield

[Thomas Gleixner]

Jacob,

On Fri, 14 May 2010, Jacob Pan wrote:

> Medfield is the follow-up of Moorestown, it is treated under the same
> HW sub-architecture. However, we do need to know the CPU type such that
> some drivers can act accordingly.
> 
> We also have different optimal clock configuration for each CPU type.
> For Moorestown the CPU type is Lincroft and for Medfield the CPU type is
> Penwell.
> 
> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
> ---
>  arch/x86/include/asm/mrst.h |   13 +++++++++++++
>  arch/x86/kernel/mrst.c      |   21 +++++++++++++++++++++
>  2 files changed, 34 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/x86/include/asm/mrst.h b/arch/x86/include/asm/mrst.h
> index 451d30e..ddf0ad8 100644
> --- a/arch/x86/include/asm/mrst.h
> +++ b/arch/x86/include/asm/mrst.h
> @@ -11,8 +11,21 @@
>  #ifndef _ASM_X86_MRST_H
>  #define _ASM_X86_MRST_H
>  extern int pci_mrst_init(void);
> +extern int mrst_identify_cpu(void);
>  int __init sfi_parse_mrtc(struct sfi_table_header *table);
>  
> +/**
> + * Medfield is the follow-up of Moorestown, it combines two chip solution into
> + * one. Other than that it also added always-on and constant tsc and lapic
> + * timers. Medfield is the platform name, and the chip name is called Penwell
> + * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
> + * identified via MSRs.
> + */
> +enum mrst_cpu_type {
> +	MRST_CPU_CHIP_LINCROFT = 1,
> +	MRST_CPU_CHIP_PENWELL,
> +};
> +
>  #define SFI_MTMR_MAX_NUM 8
>  #define SFI_MRTC_MAX	8
>  
> diff --git a/arch/x86/kernel/mrst.c b/arch/x86/kernel/mrst.c
> index 0aad867..a3e85be 100644
> --- a/arch/x86/kernel/mrst.c
> +++ b/arch/x86/kernel/mrst.c
> @@ -27,6 +27,7 @@
>  
>  static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
>  static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
> +static u32 mrst_cpu_chip;
>  int sfi_mtimer_num;
>  
>  struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
> @@ -216,6 +217,26 @@ static void __init mrst_setup_boot_clock(void)
>  		setup_boot_APIC_clock();
>  };
>  
> +int mrst_identify_cpu(void)
> +{
> +	if (boot_cpu_data.x86 == 6 &&
> +		boot_cpu_data.x86_model == 0x27 &&
> +		boot_cpu_data.x86_mask == 1)
> +		mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;
> +	else if (boot_cpu_data.x86 == 6 &&
> +		boot_cpu_data.x86_model == 0x26)
> +		mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
> +	else {
> +		pr_err("Unknown Moorestown CPU type, default to Lincroft\n");
> +		mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
> +	}
> +	pr_debug("Moorestown CPU %s identified\n",
> +		(mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) ?
> +		"Lincroft" : "Penwell");
> +
> +	return mrst_cpu_chip;
> +}

Why are you having mrst_cpu_chip as a caching variable if you expose
the identify function ? Either you evaluate boot_cpu_data everytime or
you do it once and expose a function which lets you access the cached
data. IIRC Alan mentioned that drivers need this info, so the access
function will need an EXPORT_SYMBOL_GPL to work.

Thanks,

	tglx

Re: [PATCH 2/8] x86/mrst: add cpu type detection for Medfield

[jacob pan]

>
>Why are you having mrst_cpu_chip as a caching variable if you expose
>the identify function ? Either you evaluate boot_cpu_data everytime or
>you do it once and expose a function which lets you access the cached
>data. IIRC Alan mentioned that drivers need this info, so the access
>function will need an EXPORT_SYMBOL_GPL to work.
>

I cached value because mrst_cpu_chip is used a few times in mrst.c, I should
fix that to have a unified interface. will also do the EXPORT_SYMBOL_GPL.

thanks.

[PATCH 3/8] x86/mrst: add more timer options to include Medfield

[Jacob Pan]

Medfield has added always-on lapic timer which will be ranked higher
than the platform timers. This patch allows more timer options to
support optimal configuration for both Moorestown and Medfield.

i.e. per CPU always-on lapic timers for Medfield
     per CPU APB timers for Moorestown

Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
---
 arch/x86/include/asm/mrst.h |    7 ++++++
 arch/x86/kernel/mrst.c      |   51 +++++++++++++++++++++++++++++++++++-------
 2 files changed, 49 insertions(+), 9 deletions(-)

diff --git a/arch/x86/include/asm/mrst.h b/arch/x86/include/asm/mrst.h
index ddf0ad8..f683603 100644
--- a/arch/x86/include/asm/mrst.h
+++ b/arch/x86/include/asm/mrst.h
@@ -12,6 +12,7 @@
 #define _ASM_X86_MRST_H
 extern int pci_mrst_init(void);
 extern int mrst_identify_cpu(void);
+extern int mrst_timer_options __cpuinitdata;
 int __init sfi_parse_mrtc(struct sfi_table_header *table);
 
 /**
@@ -26,6 +27,12 @@ enum mrst_cpu_type {
 	MRST_CPU_CHIP_PENWELL,
 };
 
+enum mrst_timer_options {
+	MRST_TIMER_DEFAULT,
+	MRST_TIMER_APBT_ONLY,
+	MRST_TIMER_LAPIC_APBT,
+};
+
 #define SFI_MTMR_MAX_NUM 8
 #define SFI_MRTC_MAX	8
 
diff --git a/arch/x86/kernel/mrst.c b/arch/x86/kernel/mrst.c
index a3e85be..339d7f5 100644
--- a/arch/x86/kernel/mrst.c
+++ b/arch/x86/kernel/mrst.c
@@ -25,6 +25,29 @@
 #include <asm/i8259.h>
 #include <asm/apb_timer.h>
 
+/**
+ * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
+ * cmdline option x86_mrst_timer can be used to override the configuration
+ * to prefer one or the other.
+ * at runtime, there are basically three timer configurations:
+ * 1. per cpu apbt clock only
+ * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only
+ * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast.
+ *
+ * by default (without cmdline option), platform code first detects cpu type
+ * to see if we are on lincroft or penwell, then set up both lapic or apbt
+ * clocks accordingly.
+ * i.e. by default, medfield uses configuration #2, moorestown uses #1.
+ * config #3 is supported but not recommended on medfield.
+ *
+ * rating and feature summary:
+ * lapic (with C3STOP) --------- 100
+ * apbt (always-on) ------------ 110
+ * lapic (always-on,ARAT) ------ 150
+ */
+
+int mrst_timer_options __cpuinitdata;
+
 static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
 static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
 static u32 mrst_cpu_chip;
@@ -168,15 +191,16 @@ int __init sfi_parse_mrtc(struct sfi_table_header *table)
 	return 0;
 }
 
-/*
- * the secondary clock in Moorestown can be APBT or LAPIC clock, default to
- * APBT but cmdline option can also override it.
- */
 static void __cpuinit mrst_setup_secondary_clock(void)
 {
-	/* restore default lapic clock if disabled by cmdline */
-	if (disable_apbt_percpu)
-		return setup_secondary_APIC_clock();
+	if ((mrst_timer_options == MRST_TIMER_APBT_ONLY))
+		return apbt_setup_secondary_clock();
+	if (cpu_has(&current_cpu_data, X86_FEATURE_ARAT)
+		||  (mrst_timer_options == MRST_TIMER_LAPIC_APBT)) {
+		pr_info("using lapic timers for secondary clock\n");
+		setup_secondary_APIC_clock();
+		return;
+	}
 	apbt_setup_secondary_clock();
 }
 
@@ -196,6 +220,13 @@ static unsigned long __init mrst_calibrate_tsc(void)
 
 void __init mrst_time_init(void)
 {
+	mrst_identify_cpu();
+
+	/* if cpu is penwell, lapic timer will be used by default */
+	if ((mrst_cpu_chip == MRST_CPU_CHIP_PENWELL) &&
+		(mrst_timer_options == MRST_TIMER_DEFAULT))
+		return;
+
 	sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
 	pre_init_apic_IRQ0();
 	apbt_time_init();
@@ -212,8 +243,10 @@ void __init mrst_rtc_init(void)
  */
 static void __init mrst_setup_boot_clock(void)
 {
-	pr_info("%s: per cpu apbt flag %d \n", __func__, disable_apbt_percpu);
-	if (disable_apbt_percpu)
+	if (mrst_timer_options == MRST_TIMER_APBT_ONLY)
+		return;
+	if ((mrst_timer_options == MRST_TIMER_LAPIC_APBT)
+		|| (mrst_cpu_chip == MRST_CPU_CHIP_PENWELL))
 		setup_boot_APIC_clock();
 };
 
-- 
1.6.3.3

Re: [PATCH 3/8] x86/mrst: add more timer options to include Medfield

[Thomas Gleixner]

On Fri, 14 May 2010, Jacob Pan wrote:
>  
> -/*
> - * the secondary clock in Moorestown can be APBT or LAPIC clock, default to
> - * APBT but cmdline option can also override it.
> - */
>  static void __cpuinit mrst_setup_secondary_clock(void)
>  {
> -	/* restore default lapic clock if disabled by cmdline */
> -	if (disable_apbt_percpu)
> -		return setup_secondary_APIC_clock();
> +	if ((mrst_timer_options == MRST_TIMER_APBT_ONLY))
> +		return apbt_setup_secondary_clock();

  Did you compile this ?

> +	if (cpu_has(&current_cpu_data, X86_FEATURE_ARAT)
> +		||  (mrst_timer_options == MRST_TIMER_LAPIC_APBT)) {
> +		pr_info("using lapic timers for secondary clock\n");
> +		setup_secondary_APIC_clock();
> +		return;
> +	}

  As I said before, this function sucks. The decision logic is just
  obscure. It's not rocket science to make it understandable.

>  	apbt_setup_secondary_clock();
>  }

Thanks,

	tglx

[PATCH 4/8] x86/apbt: support more timer configurations on mrst

[Jacob Pan]

From: Jacob Pan <jacob.jun.pan@intel.com>

With the addition of Medfield as a follow-up of Moorestown, more timer
configurations are available to the kernel. This patch allows the
optimal default configuration to be chosen and overwritten by cmdline
as well.
i.e. For Moorestown, percpu APB timers are default. For Medfield local
always-on local APIC timers are default (w/o any platform timers).

Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
---
 arch/x86/include/asm/apb_timer.h |    2 +-
 arch/x86/kernel/apb_timer.c      |   18 ++++++++++--------
 2 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/arch/x86/include/asm/apb_timer.h b/arch/x86/include/asm/apb_timer.h
index c74a2ee..4127fd1 100644
--- a/arch/x86/include/asm/apb_timer.h
+++ b/arch/x86/include/asm/apb_timer.h
@@ -55,7 +55,7 @@ extern unsigned long apbt_quick_calibrate(void);
 extern int arch_setup_apbt_irqs(int irq, int trigger, int mask, int cpu);
 extern void apbt_setup_secondary_clock(void);
 extern unsigned int boot_cpu_id;
-extern int disable_apbt_percpu;
+extern int mrst_timer_options;
 
 extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint);
 extern void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr);
diff --git a/arch/x86/kernel/apb_timer.c b/arch/x86/kernel/apb_timer.c
index a353475..08dfbf8 100644
--- a/arch/x86/kernel/apb_timer.c
+++ b/arch/x86/kernel/apb_timer.c
@@ -43,10 +43,11 @@
 
 #include <asm/fixmap.h>
 #include <asm/apb_timer.h>
+#include <asm/mrst.h>
 
 #define APBT_MASK			CLOCKSOURCE_MASK(32)
 #define APBT_SHIFT			22
-#define APBT_CLOCKEVENT_RATING		150
+#define APBT_CLOCKEVENT_RATING		110
 #define APBT_CLOCKSOURCE_RATING		250
 #define APBT_MIN_DELTA_USEC		200
 
@@ -83,8 +84,6 @@ struct apbt_dev {
 	char name[10];
 };
 
-int disable_apbt_percpu __cpuinitdata;
-
 static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev);
 
 #ifdef CONFIG_SMP
@@ -204,9 +203,9 @@ static inline int __init setup_x86_mrst_timer(char *arg)
 		return -EINVAL;
 
 	if (strcmp("apbt_only", arg) == 0)
-		disable_apbt_percpu = 0;
+		mrst_timer_options = MRST_TIMER_APBT_ONLY;
 	else if (strcmp("lapic_and_apbt", arg) == 0)
-		disable_apbt_percpu = 1;
+		mrst_timer_options = MRST_TIMER_LAPIC_APBT;
 	else {
 		pr_warning("X86 MRST timer option %s not recognised"
 			   " use x86_mrst_timer=apbt_only or lapic_and_apbt\n",
@@ -335,7 +334,7 @@ static int __init apbt_clockevent_register(void)
 	adev->num = smp_processor_id();
 	memcpy(&adev->evt, &apbt_clockevent, sizeof(struct clock_event_device));
 
-	if (disable_apbt_percpu) {
+	if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
 		apbt_clockevent.rating = APBT_CLOCKEVENT_RATING - 100;
 		global_clock_event = &adev->evt;
 		printk(KERN_DEBUG "%s clockevent registered as global\n",
@@ -429,7 +428,8 @@ static int apbt_cpuhp_notify(struct notifier_block *n,
 
 static __init int apbt_late_init(void)
 {
-	if (disable_apbt_percpu || !apb_timer_block_enabled)
+	if (mrst_timer_options == MRST_TIMER_LAPIC_APBT ||
+		!apb_timer_block_enabled)
 		return 0;
 	/* This notifier should be called after workqueue is ready */
 	hotcpu_notifier(apbt_cpuhp_notify, -20);
@@ -450,6 +450,8 @@ static void apbt_set_mode(enum clock_event_mode mode,
 	int timer_num;
 	struct apbt_dev *adev = EVT_TO_APBT_DEV(evt);
 
+	BUG_ON(!apbt_virt_address);
+
 	timer_num = adev->num;
 	pr_debug("%s CPU %d timer %d mode=%d\n",
 		 __func__, first_cpu(*evt->cpumask), timer_num, mode);
@@ -676,7 +678,7 @@ void __init apbt_time_init(void)
 	}
 #ifdef CONFIG_SMP
 	/* kernel cmdline disable apb timer, so we will use lapic timers */
-	if (disable_apbt_percpu) {
+	if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
 		printk(KERN_INFO "apbt: disabled per cpu timer\n");
 		return;
 	}
-- 
1.6.3.3

Re: [PATCH 4/8] x86/apbt: support more timer configurations on mrst

[Thomas Gleixner]

On Fri, 14 May 2010, Jacob Pan wrote:
>  
> -int disable_apbt_percpu __cpuinitdata;
> -
>  static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev);
>  
>  #ifdef CONFIG_SMP
> @@ -204,9 +203,9 @@ static inline int __init setup_x86_mrst_timer(char *arg)
>  		return -EINVAL;
>  
>  	if (strcmp("apbt_only", arg) == 0)
> -		disable_apbt_percpu = 0;
> +		mrst_timer_options = MRST_TIMER_APBT_ONLY;
>  	else if (strcmp("lapic_and_apbt", arg) == 0)
> -		disable_apbt_percpu = 1;
> +		mrst_timer_options = MRST_TIMER_LAPIC_APBT;

  You changed the selection from disable_apbt_percpu to
  mrst_timer_options in the previous patch and now you change the
  command line options to take effect.

  That means the previous patch is not testable by itself. Neither is
  the current one, so there is no point in having separate
  patches. Please fold them into one.

Thanks,

	tglx

[PATCH 5/8] x86/platform: add a wallclock_init func to x86_platforms ops

[Jacob Pan]

From: Feng Tang <feng.tang@intel.com>

Some wall clock devices use MMIO based HW register, this new function will
give them a chance to do some initialization work before their get/set_time
service get called.

Signed-off-by: Feng Tang <feng.tang@intel.com>
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
---
 arch/x86/include/asm/x86_init.h |    2 ++
 arch/x86/kernel/setup.c         |    2 ++
 arch/x86/kernel/x86_init.c      |    2 ++
 3 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
index 519b543..be027a8 100644
--- a/arch/x86/include/asm/x86_init.h
+++ b/arch/x86/include/asm/x86_init.h
@@ -138,6 +138,7 @@ struct x86_cpuinit_ops {
 /**
  * struct x86_platform_ops - platform specific runtime functions
  * @calibrate_tsc:		calibrate TSC
+ * @wallclock_init:		init the wallclock device
  * @get_wallclock:		get time from HW clock like RTC etc.
  * @set_wallclock:		set time back to HW clock
  * @is_untracked_pat_range	exclude from PAT logic
@@ -145,6 +146,7 @@ struct x86_cpuinit_ops {
  */
 struct x86_platform_ops {
 	unsigned long (*calibrate_tsc)(void);
+	void (*wallclock_init)(void);
 	unsigned long (*get_wallclock)(void);
 	int (*set_wallclock)(unsigned long nowtime);
 	void (*iommu_shutdown)(void);
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index c4851ef..d001d8c 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -1050,6 +1050,8 @@ void __init setup_arch(char **cmdline_p)
 #endif
 	x86_init.oem.banner();
 
+	x86_platform.wallclock_init();
+
 	mcheck_init();
 }
 
diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
index 61a1e8c..ee00d76 100644
--- a/arch/x86/kernel/x86_init.c
+++ b/arch/x86/kernel/x86_init.c
@@ -24,6 +24,7 @@ void __init x86_init_uint_noop(unsigned int unused) { }
 void __init x86_init_pgd_noop(pgd_t *unused) { }
 int __init iommu_init_noop(void) { return 0; }
 void iommu_shutdown_noop(void) { }
+void wallclock_init_noop(void) { }
 
 /*
  * The platform setup functions are preset with the default functions
@@ -88,6 +89,7 @@ static void default_nmi_init(void) { };
 
 struct x86_platform_ops x86_platform = {
 	.calibrate_tsc			= native_calibrate_tsc,
+	.wallclock_init			= wallclock_init_noop,
 	.get_wallclock			= mach_get_cmos_time,
 	.set_wallclock			= mach_set_rtc_mmss,
 	.iommu_shutdown			= iommu_shutdown_noop,
-- 
1.6.3.3

Re: [PATCH 5/8] x86/platform: add a wallclock_init func to x86_platforms ops

[Thomas Gleixner]

On Fri, 14 May 2010, Jacob Pan wrote:

> From: Feng Tang <feng.tang@intel.com>
> 
> Some wall clock devices use MMIO based HW register, this new function will
> give them a chance to do some initialization work before their get/set_time
> service get called.

NAK. This is the very same patch I reviewed in detail a week
ago. Please fix it.

Thanks,

	tglx

[PATCH 6/8] x86/mrst: add vrtc driver which serves as a wall clock device

[Jacob Pan]

From: Feng Tang <feng.tang@intel.com>

Moorestown platform doesn't have a m146818 RTC device like traditional
x86 PC, but a firmware emulated virtual RTC device(vrtc), which provides
some basic RTC functions like get/set time. vrtc serves as the only
wall clock device on Moorestown platform.

Signed-off-by: Feng Tang <feng.tang@intel.com>
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
---
 arch/x86/include/asm/fixmap.h |    4 ++
 arch/x86/include/asm/vrtc.h   |   27 +++++++++++
 arch/x86/kernel/Makefile      |    2 +-
 arch/x86/kernel/mrst.c        |   20 ++++++++
 arch/x86/kernel/vrtc.c        |  100 +++++++++++++++++++++++++++++++++++++++++
 5 files changed, 152 insertions(+), 1 deletions(-)
 create mode 100644 arch/x86/include/asm/vrtc.h
 create mode 100644 arch/x86/kernel/vrtc.c

diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h
index d07b44f..c4ba8d9 100644
--- a/arch/x86/include/asm/fixmap.h
+++ b/arch/x86/include/asm/fixmap.h
@@ -117,6 +117,10 @@ enum fixed_addresses {
 	FIX_TEXT_POKE1,	/* reserve 2 pages for text_poke() */
 	FIX_TEXT_POKE0, /* first page is last, because allocation is backward */
 	__end_of_permanent_fixed_addresses,
+
+#ifdef	CONFIG_X86_MRST
+	FIX_LNW_VRTC,
+#endif
 	/*
 	 * 256 temporary boot-time mappings, used by early_ioremap(),
 	 * before ioremap() is functional.
diff --git a/arch/x86/include/asm/vrtc.h b/arch/x86/include/asm/vrtc.h
new file mode 100644
index 0000000..4e40129
--- /dev/null
+++ b/arch/x86/include/asm/vrtc.h
@@ -0,0 +1,27 @@
+#ifndef _MRST_VRTC_H
+#define _MRST_VRTC_H
+
+#ifdef CONFIG_X86_MRST
+extern unsigned char vrtc_cmos_read(unsigned char reg);
+extern void vrtc_cmos_write(unsigned char val, unsigned char reg);
+extern unsigned long vrtc_get_time(void);
+extern int vrtc_set_mmss(unsigned long nowtime);
+extern void vrtc_set_base(void __iomem *base);
+
+#define MRST_VRTC_PGOFFSET  (0xc00)
+
+#else
+static inline unsigned char vrtc_cmos_read(unsigned char reg)
+{
+	return 0xff;
+}
+
+static inline void vrtc_cmos_write(unsigned char val, unsigned char reg)
+{
+	return;
+}
+#endif
+
+#define MRST_VRTC_MAP_SZ	(1024)
+
+#endif
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index e77b220..f3fdcbe 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -104,7 +104,7 @@ obj-$(CONFIG_SCx200)		+= scx200.o
 scx200-y			+= scx200_32.o
 
 obj-$(CONFIG_OLPC)		+= olpc.o
-obj-$(CONFIG_X86_MRST)		+= mrst.o
+obj-$(CONFIG_X86_MRST)		+= mrst.o vrtc.o
 
 microcode-y				:= microcode_core.o
 microcode-$(CONFIG_MICROCODE_INTEL)	+= microcode_intel.o
diff --git a/arch/x86/kernel/mrst.c b/arch/x86/kernel/mrst.c
index 339d7f5..83c23d6 100644
--- a/arch/x86/kernel/mrst.c
+++ b/arch/x86/kernel/mrst.c
@@ -24,6 +24,7 @@
 #include <asm/io.h>
 #include <asm/i8259.h>
 #include <asm/apb_timer.h>
+#include <asm/vrtc.h>
 
 /**
  * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
@@ -234,7 +235,24 @@ void __init mrst_time_init(void)
 
 void __init mrst_rtc_init(void)
 {
+	unsigned long rtc_paddr;
+	void __iomem *virt_base;
+
 	sfi_table_parse(SFI_SIG_MRTC, NULL, NULL, sfi_parse_mrtc);
+	if (!sfi_mrtc_num)
+		return;
+
+	rtc_paddr = sfi_mrtc_array[0].phys_addr;
+
+	/* vRTC's register address may not be page aligned */
+	set_fixmap_nocache(FIX_LNW_VRTC, rtc_paddr);
+
+	virt_base = (void __iomem *)__fix_to_virt(FIX_LNW_VRTC);
+	virt_base += rtc_paddr & ~PAGE_MASK;
+	vrtc_set_base(virt_base);
+
+	x86_platform.get_wallclock = vrtc_get_time;
+	x86_platform.set_wallclock = vrtc_set_mmss;
 }
 
 /*
@@ -287,6 +305,8 @@ void __init x86_mrst_early_setup(void)
 	x86_cpuinit.setup_percpu_clockev = mrst_setup_secondary_clock;
 
 	x86_platform.calibrate_tsc = mrst_calibrate_tsc;
+	x86_platform.wallclock_init = mrst_rtc_init;
+
 	x86_init.pci.init = pci_mrst_init;
 	x86_init.pci.fixup_irqs = x86_init_noop;
 
diff --git a/arch/x86/kernel/vrtc.c b/arch/x86/kernel/vrtc.c
new file mode 100644
index 0000000..fa1eb63
--- /dev/null
+++ b/arch/x86/kernel/vrtc.c
@@ -0,0 +1,100 @@
+/*
+ * vrtc.c: Driver for virtual RTC device on Intel MID platform
+ *
+ * (C) Copyright 2009 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2
+ * of the License.
+ *
+ * Note:
+ * VRTC is emulated by system controller firmware, the real HW
+ * RTC is located in the PMIC device. SCU FW shadows PMIC RTC
+ * in a memory mapped IO space that is visible to the host IA
+ * processor.
+ *
+ * This driver is based on RTC CMOS driver.
+ */
+
+#include <linux/kernel.h>
+
+#include <asm/vrtc.h>
+#include <asm/time.h>
+#include <asm/fixmap.h>
+
+static unsigned char __iomem *vrtc_virt_base;
+
+void vrtc_set_base(void __iomem *base)
+{
+	vrtc_virt_base = base;
+}
+
+unsigned char vrtc_cmos_read(unsigned char reg)
+{
+	unsigned char retval;
+
+	/* vRTC's registers range from 0x0 to 0xD */
+	if (reg > 0xd || !vrtc_virt_base)
+		return 0xff;
+
+	lock_cmos_prefix(reg);
+	retval = __raw_readb(vrtc_virt_base + (reg << 2));
+	lock_cmos_suffix(reg);
+	return retval;
+}
+EXPORT_SYMBOL(vrtc_cmos_read);
+
+void vrtc_cmos_write(unsigned char val, unsigned char reg)
+{
+	if (reg > 0xd || !vrtc_virt_base)
+		return;
+
+	lock_cmos_prefix(reg);
+	__raw_writeb(val, vrtc_virt_base + (reg << 2));
+	lock_cmos_suffix(reg);
+}
+EXPORT_SYMBOL(vrtc_cmos_write);
+
+unsigned long vrtc_get_time(void)
+{
+	u8 sec, min, hour, mday, mon;
+	u32 year;
+
+	while ((vrtc_cmos_read(RTC_FREQ_SELECT) & RTC_UIP))
+		cpu_relax();
+
+	sec = vrtc_cmos_read(RTC_SECONDS);
+	min = vrtc_cmos_read(RTC_MINUTES);
+	hour = vrtc_cmos_read(RTC_HOURS);
+	mday = vrtc_cmos_read(RTC_DAY_OF_MONTH);
+	mon = vrtc_cmos_read(RTC_MONTH);
+	year = vrtc_cmos_read(RTC_YEAR);
+
+	/* vRTC YEAR reg contains the offset to 1960 */
+	year += 1960;
+
+	printk(KERN_INFO "vRTC: sec: %d min: %d hour: %d day: %d "
+		"mon: %d year: %d\n", sec, min, hour, mday, mon, year);
+
+	return mktime(year, mon, mday, hour, min, sec);
+}
+
+/* Only care about the minutes and seconds */
+int vrtc_set_mmss(unsigned long nowtime)
+{
+	int real_sec, real_min;
+	int vrtc_min;
+
+	vrtc_min = vrtc_cmos_read(RTC_MINUTES);
+
+	real_sec = nowtime % 60;
+	real_min = nowtime / 60;
+	if (((abs(real_min - vrtc_min) + 15)/30) & 1)
+		real_min += 30;
+	real_min %= 60;
+
+	vrtc_cmos_write(real_sec, RTC_SECONDS);
+	vrtc_cmos_write(real_min, RTC_MINUTES);
+	return 0;
+}
-- 
1.6.3.3

Re: [PATCH 6/8] x86/mrst: add vrtc driver which serves as a wall clock device

[Thomas Gleixner]

On Fri, 14 May 2010, Jacob Pan wrote:

> From: Feng Tang <feng.tang@intel.com>
> 
> Moorestown platform doesn't have a m146818 RTC device like traditional
> x86 PC, but a firmware emulated virtual RTC device(vrtc), which provides
> some basic RTC functions like get/set time. vrtc serves as the only
> wall clock device on Moorestown platform.

NAK for the very same reason as [5/8]

Thanks,

	tglx

[PATCH 7/8] x86/mrst: add nop functions to x86_init mpparse functions

[Jacob Pan]

Moorestown does not have BIOS provided MP tables, we can save some time
by avoiding scaning of these tables. e.g.
[    0.000000] Scan SMP from c0000000 for 1024 bytes.
[    0.000000] Scan SMP from c009fc00 for 1024 bytes.
[    0.000000] Scan SMP from c00f0000 for 65536 bytes.
[    0.000000] Scan SMP from c00bfff0 for 1024 bytes.

Searching EBDA with the base at 0x40E will also result in random pointer
deferencing within 1MB. This can be a problem in Lincroft if the pointer
hits VGA area and VGA mode is not enabled.

Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
---
 arch/x86/kernel/mrst.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/mrst.c b/arch/x86/kernel/mrst.c
index 83c23d6..9b62d32 100644
--- a/arch/x86/kernel/mrst.c
+++ b/arch/x86/kernel/mrst.c
@@ -311,4 +311,9 @@ void __init x86_mrst_early_setup(void)
 	x86_init.pci.fixup_irqs = x86_init_noop;
 
 	legacy_pic = &null_legacy_pic;
+
+	/* Avoid searching for BIOS MP tables */
+	x86_init.mpparse.find_smp_config = x86_init_noop;
+	x86_init.mpparse.get_smp_config = x86_init_uint_noop;
+
 }
-- 
1.6.3.3

Re: [PATCH 7/8] x86/mrst: add nop functions to x86_init mpparse functions

[Thomas Gleixner]

On Fri, 14 May 2010, Jacob Pan wrote:

> Moorestown does not have BIOS provided MP tables, we can save some time
> by avoiding scaning of these tables. e.g.
> [    0.000000] Scan SMP from c0000000 for 1024 bytes.
> [    0.000000] Scan SMP from c009fc00 for 1024 bytes.
> [    0.000000] Scan SMP from c00f0000 for 65536 bytes.
> [    0.000000] Scan SMP from c00bfff0 for 1024 bytes.
> 
> Searching EBDA with the base at 0x40E will also result in random pointer
> deferencing within 1MB. This can be a problem in Lincroft if the pointer
> hits VGA area and VGA mode is not enabled.
> 
> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>

Acked-by: Thomas Gleixner <tglx@linutronix.de>

> ---
>  arch/x86/kernel/mrst.c |    5 +++++
>  1 files changed, 5 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/x86/kernel/mrst.c b/arch/x86/kernel/mrst.c
> index 83c23d6..9b62d32 100644
> --- a/arch/x86/kernel/mrst.c
> +++ b/arch/x86/kernel/mrst.c
> @@ -311,4 +311,9 @@ void __init x86_mrst_early_setup(void)
>  	x86_init.pci.fixup_irqs = x86_init_noop;
>  
>  	legacy_pic = &null_legacy_pic;
> +
> +	/* Avoid searching for BIOS MP tables */
> +	x86_init.mpparse.find_smp_config = x86_init_noop;
> +	x86_init.mpparse.get_smp_config = x86_init_uint_noop;
> +
>  }
> -- 
> 1.6.3.3
> 

[tip:x86/mrst] x86, mrst: add nop functions to x86_init mpparse functions

[tip-bot for Jacob Pan]

Commit-ID:  fea24e28c663e62663097f0ed3b8ff1f9a87f15e
Gitweb:     http://git.kernel.org/tip/fea24e28c663e62663097f0ed3b8ff1f9a87f15e
Author:     Jacob Pan <jacob.jun.pan@linux.intel.com>
AuthorDate: Fri, 14 May 2010 14:41:20 -0700
Committer:  H. Peter Anvin <hpa@linux.intel.com>
CommitDate: Sun, 16 May 2010 22:47:41 -0700

x86, mrst: add nop functions to x86_init mpparse functions

Moorestown does not have BIOS provided MP tables, we can save some time
by avoiding scaning of these tables. e.g.
[    0.000000] Scan SMP from c0000000 for 1024 bytes.
[    0.000000] Scan SMP from c009fc00 for 1024 bytes.
[    0.000000] Scan SMP from c00f0000 for 65536 bytes.
[    0.000000] Scan SMP from c00bfff0 for 1024 bytes.

Searching EBDA with the base at 0x40E will also result in random pointer
deferencing within 1MB. This can be a problem in Lincroft if the pointer
hits VGA area and VGA mode is not enabled.

Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
LKML-Reference: <1273873281-17489-8-git-send-email-jacob.jun.pan@linux.intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
---
 arch/x86/kernel/mrst.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/mrst.c b/arch/x86/kernel/mrst.c
index 0aad867..e796448 100644
--- a/arch/x86/kernel/mrst.c
+++ b/arch/x86/kernel/mrst.c
@@ -237,4 +237,9 @@ void __init x86_mrst_early_setup(void)
 	x86_init.pci.fixup_irqs = x86_init_noop;
 
 	legacy_pic = &null_legacy_pic;
+
+	/* Avoid searching for BIOS MP tables */
+	x86_init.mpparse.find_smp_config = x86_init_noop;
+	x86_init.mpparse.get_smp_config = x86_init_uint_noop;
+
 }

[PATCH 8/8] input: do not select i8042 for x86 mid

[Jacob Pan]

From: Jacob Pan <jacob.jun.pan@intel.com>

Moorestown does not have i8042 based keyboard controller, so give
an option to deselect i8042 for non-pc mid

Signed-off-by: Jacob Pan <jacob.jun.pan@intel.com>
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
---
 drivers/input/keyboard/Kconfig |    2 +-
 drivers/input/mouse/Kconfig    |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index 64c1023..42aa650 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -73,7 +73,7 @@ config KEYBOARD_ATKBD
 	default y
 	select SERIO
 	select SERIO_LIBPS2
-	select SERIO_I8042 if X86
+	select SERIO_I8042 if X86 && !X86_MRST
 	select SERIO_GSCPS2 if GSC
 	help
 	  Say Y here if you want to use a standard AT or PS/2 keyboard. Usually
diff --git a/drivers/input/mouse/Kconfig b/drivers/input/mouse/Kconfig
index c714ca2..eeb58c1 100644
--- a/drivers/input/mouse/Kconfig
+++ b/drivers/input/mouse/Kconfig
@@ -17,7 +17,7 @@ config MOUSE_PS2
 	default y
 	select SERIO
 	select SERIO_LIBPS2
-	select SERIO_I8042 if X86
+	select SERIO_I8042 if X86 && !X86_MRST
 	select SERIO_GSCPS2 if GSC
 	help
 	  Say Y here if you have a PS/2 mouse connected to your system. This
-- 
1.6.3.3

Re: [PATCH 8/8] input: do not select i8042 for x86 mid

[Thomas Gleixner]

On Fri, 14 May 2010, Jacob Pan wrote:

> From: Jacob Pan <jacob.jun.pan@intel.com>
> 
> Moorestown does not have i8042 based keyboard controller, so give
> an option to deselect i8042 for non-pc mid
> 
> Signed-off-by: Jacob Pan <jacob.jun.pan@intel.com>
> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>

Still sending patches to your other self ? :)

Acked-by: Thomas Gleixner <tglx@linutronix.de>

Though this patch should go via Dmitry (Cc'ed).

> ---
>  drivers/input/keyboard/Kconfig |    2 +-
>  drivers/input/mouse/Kconfig    |    2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
> index 64c1023..42aa650 100644
> --- a/drivers/input/keyboard/Kconfig
> +++ b/drivers/input/keyboard/Kconfig
> @@ -73,7 +73,7 @@ config KEYBOARD_ATKBD
>  	default y
>  	select SERIO
>  	select SERIO_LIBPS2
> -	select SERIO_I8042 if X86
> +	select SERIO_I8042 if X86 && !X86_MRST
>  	select SERIO_GSCPS2 if GSC
>  	help
>  	  Say Y here if you want to use a standard AT or PS/2 keyboard. Usually
> diff --git a/drivers/input/mouse/Kconfig b/drivers/input/mouse/Kconfig
> index c714ca2..eeb58c1 100644
> --- a/drivers/input/mouse/Kconfig
> +++ b/drivers/input/mouse/Kconfig
> @@ -17,7 +17,7 @@ config MOUSE_PS2
>  	default y
>  	select SERIO
>  	select SERIO_LIBPS2
> -	select SERIO_I8042 if X86
> +	select SERIO_I8042 if X86 && !X86_MRST
>  	select SERIO_GSCPS2 if GSC
>  	help
>  	  Say Y here if you have a PS/2 mouse connected to your system. This
> -- 
> 1.6.3.3
> 

Re: [PATCH 8/8] input: do not select i8042 for x86 mid

[H. Peter Anvin]

On 05/16/2010 03:48 PM, Thomas Gleixner wrote:
> On Fri, 14 May 2010, Jacob Pan wrote:
> 
>> From: Jacob Pan <jacob.jun.pan@intel.com>
>>
>> Moorestown does not have i8042 based keyboard controller, so give
>> an option to deselect i8042 for non-pc mid
>>
>> Signed-off-by: Jacob Pan <jacob.jun.pan@intel.com>
>> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
> 
> Still sending patches to your other self ? :)
> 
> Acked-by: Thomas Gleixner <tglx@linutronix.de>
> 
> Though this patch should go via Dmitry (Cc'ed).
> 

Dmitry -- let us know if you want us to take this patch via -tip,
otherwise I'll assume you are handling it.

	-hpa

-- 
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel.  I don't speak on their behalf.

Re: [PATCH 8/8] input: do not select i8042 for x86 mid

[jacob pan]

Thomas Gleixner Mon, 17 May 2010 00:48:15 +0200 (CEST)

>> Signed-off-by: Jacob Pan <jacob.jun.pan@intel.com>
>> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
>
>Still sending patches to your other self ? :)
>
just resent the patch without duplicated email address. sorry, trying to migrated away from my outlook email account.