[PATCH 0/2] v3 Moorestown clock related patches

[PATCH 0/2] v3 Moorestown clock related patches

[Jacob Pan]

Hi,
Please review the two patches related Moorestown/Medfield clock selection
logic. tglx has suggested a much cleaner logic in
http://lkml.org/lkml/2010/5/17/406
So patch #2 is the implementation of new logic plus small tweaks based on
testing results.
I also dropped x86_mask check for Penwell CPU check. It is not needed, CPU
family and model should be sufficient/accurate to identify Lincroft vs
Penwell.

*** BLURB HERE ***

Jacob Pan (2):
  x86/mrst: add cpu type detection
  x86/mrst: add more timer config options

 arch/x86/include/asm/apb_timer.h |    1 -
 arch/x86/include/asm/mrst.h      |   20 +++++++
 arch/x86/kernel/apb_timer.c      |   37 +++----------
 arch/x86/kernel/mrst.c           |  109 ++++++++++++++++++++++++++++++--------
 4 files changed, 114 insertions(+), 53 deletions(-)

[PATCH 1/2] v4 x86/mrst: add cpu type detection

[Jacob Pan]

Medfield is the follow-up of Moorestown, it is treated under the same
HW sub-architecture. However, we do need to know the CPU type in order
for some of the driver to act accordingly.
We also have different optimal clock configuration for each CPU type.

Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
---
 arch/x86/include/asm/mrst.h |   19 +++++++++++++++++++
 arch/x86/kernel/mrst.c      |   20 ++++++++++++++++++++
 2 files changed, 39 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/mrst.h b/arch/x86/include/asm/mrst.h
index 451d30e..a25eff3 100644
--- a/arch/x86/include/asm/mrst.h
+++ b/arch/x86/include/asm/mrst.h
@@ -11,8 +11,27 @@
 #ifndef _ASM_X86_MRST_H
 #define _ASM_X86_MRST_H
 extern int pci_mrst_init(void);
+extern int mrst_identify_cpu(void);
 int __init sfi_parse_mrtc(struct sfi_table_header *table);
 
+/**
+ * Medfield is the follow-up of Moorestown, it combines two chip solution into
+ * one. Other than that it also added always-on and constant tsc and lapic
+ * timers. Medfield is the platform name, and the chip name is called Penwell
+ * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
+ * identified via MSRs.
+ */
+enum mrst_cpu_type {
+	MRST_CPU_CHIP_LINCROFT = 1,
+	MRST_CPU_CHIP_PENWELL,
+};
+
+enum mrst_timer_options {
+	MRST_TIMER_DEFAULT,
+	MRST_TIMER_APBT_ONLY,
+	MRST_TIMER_LAPIC_APBT,
+};
+
 #define SFI_MTMR_MAX_NUM 8
 #define SFI_MRTC_MAX	8
 
diff --git a/arch/x86/kernel/mrst.c b/arch/x86/kernel/mrst.c
index 0aad867..0bca837 100644
--- a/arch/x86/kernel/mrst.c
+++ b/arch/x86/kernel/mrst.c
@@ -216,6 +216,26 @@ static void __init mrst_setup_boot_clock(void)
 		setup_boot_APIC_clock();
 };
 
+int mrst_identify_cpu(void)
+{
+	u32 mrst_cpu_chip;
+
+	if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
+		mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;
+	else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x26)
+		mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
+	else {
+		pr_err("Unknown Moorestown CPU (%d:%d), default to Lincroft\n",
+			boot_cpu_data.x86, boot_cpu_data.x86_model);
+		mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
+	}
+	pr_debug("Moorestown CPU %s identified\n",
+		(mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) ?
+		"Lincroft" : "Penwell");
+	return mrst_cpu_chip;
+}
+EXPORT_SYMBOL_GPL(mrst_identify_cpu);
+
 /*
  * Moorestown specific x86_init function overrides and early setup
  * calls.
-- 
1.6.3.3

Re: [PATCH 1/2] v4 x86/mrst: add cpu type detection

[Thomas Gleixner]

On Tue, 18 May 2010, Jacob Pan wrote:
>  
> +int mrst_identify_cpu(void)
> +{
> +	u32 mrst_cpu_chip;
> +
> +	if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
> +		mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;
> +	else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x26)
> +		mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
> +	else {
> +		pr_err("Unknown Moorestown CPU (%d:%d), default to Lincroft\n",
> +			boot_cpu_data.x86, boot_cpu_data.x86_model);
> +		mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
> +	}
> +	pr_debug("Moorestown CPU %s identified\n",
> +		(mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) ?
> +		"Lincroft" : "Penwell");

  Do you really want a printk for each call ?

  Aside of that wouldn't it make more sense to do the chip
  identification only once from mrst_init() and cache the result and
  change mrst_identify_cpu()

int mrst_indetify_cpu(void)
{
	return mrst_cpu_chip;
}
EXPORT_SYMBOL_GPL(mrst_identify_cpu);

I think one of your earlier versions did that, but was not consistent
in it's behaviour.

Thanks,

	tglx

Re: [PATCH 1/2] v4 x86/mrst: add cpu type detection

[jacob pan]

>  Aside of that wouldn't it make more sense to do the chip
>  identification only once from mrst_init() and cache the result and
>  change mrst_identify_cpu()
>
the problem is again the ordering of cpuid, boot_cpu_data is not available
by the time we call  x86_mrst_early_setup(). I can move it to mrst_time_init()
but not very ideal. Unless we go back to do cpuid directly in the v1 patch :).

Re: [PATCH 1/2] v4 x86/mrst: add cpu type detection

[Thomas Gleixner]

On Wed, 19 May 2010, jacob pan wrote:
> 
> >  Aside of that wouldn't it make more sense to do the chip
> >  identification only once from mrst_init() and cache the result and
> >  change mrst_identify_cpu()
> >
> the problem is again the ordering of cpuid, boot_cpu_data is not available
> by the time we call  x86_mrst_early_setup(). I can move it to mrst_time_init()

Hmm, right.

> but not very ideal. Unless we go back to do cpuid directly in the v1 patch :).

x86_init.oem.arch_setup() is the point where you can do that, that's
called after early_cpu_init() which fills boot_cpu_data. It's way
before the first user of mrst_chip.

Thanks,

	tglx

[PATCH 2/2] v4 x86/mrst: add more timer config options

[Jacob Pan]

Always-on local APIC timer (ARAT) has been introduced to Medfield, along
with the platform APB timers we have more timer configuration options
between Moorestown and Medfield.

This patch adds run-time detection of avaiable timer features so that
we can treat Medfield as a variant of Moorestown and set up the optimal
timer options for each platform. i.e.

Medfield: per cpu always-on local APIC timer
Moorestown: per cpu APB timer

Manual override is possible via cmdline option x86_mrst_timer.

Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
---
 arch/x86/include/asm/apb_timer.h |    1 -
 arch/x86/include/asm/mrst.h      |    1 +
 arch/x86/kernel/apb_timer.c      |   37 +++------------
 arch/x86/kernel/mrst.c           |   93 +++++++++++++++++++++++++++----------
 4 files changed, 77 insertions(+), 55 deletions(-)

diff --git a/arch/x86/include/asm/apb_timer.h b/arch/x86/include/asm/apb_timer.h
index c74a2ee..a69b1ac 100644
--- a/arch/x86/include/asm/apb_timer.h
+++ b/arch/x86/include/asm/apb_timer.h
@@ -55,7 +55,6 @@ extern unsigned long apbt_quick_calibrate(void);
 extern int arch_setup_apbt_irqs(int irq, int trigger, int mask, int cpu);
 extern void apbt_setup_secondary_clock(void);
 extern unsigned int boot_cpu_id;
-extern int disable_apbt_percpu;
 
 extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint);
 extern void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr);
diff --git a/arch/x86/include/asm/mrst.h b/arch/x86/include/asm/mrst.h
index a25eff3..f683603 100644
--- a/arch/x86/include/asm/mrst.h
+++ b/arch/x86/include/asm/mrst.h
@@ -12,6 +12,7 @@
 #define _ASM_X86_MRST_H
 extern int pci_mrst_init(void);
 extern int mrst_identify_cpu(void);
+extern int mrst_timer_options __cpuinitdata;
 int __init sfi_parse_mrtc(struct sfi_table_header *table);
 
 /**
diff --git a/arch/x86/kernel/apb_timer.c b/arch/x86/kernel/apb_timer.c
index a353475..8dd7780 100644
--- a/arch/x86/kernel/apb_timer.c
+++ b/arch/x86/kernel/apb_timer.c
@@ -43,10 +43,11 @@
 
 #include <asm/fixmap.h>
 #include <asm/apb_timer.h>
+#include <asm/mrst.h>
 
 #define APBT_MASK			CLOCKSOURCE_MASK(32)
 #define APBT_SHIFT			22
-#define APBT_CLOCKEVENT_RATING		150
+#define APBT_CLOCKEVENT_RATING		110
 #define APBT_CLOCKSOURCE_RATING		250
 #define APBT_MIN_DELTA_USEC		200
 
@@ -83,8 +84,6 @@ struct apbt_dev {
 	char name[10];
 };
 
-int disable_apbt_percpu __cpuinitdata;
-
 static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev);
 
 #ifdef CONFIG_SMP
@@ -195,29 +194,6 @@ static struct clock_event_device apbt_clockevent = {
 };
 
 /*
- * if user does not want to use per CPU apb timer, just give it a lower rating
- * than local apic timer and skip the late per cpu timer init.
- */
-static inline int __init setup_x86_mrst_timer(char *arg)
-{
-	if (!arg)
-		return -EINVAL;
-
-	if (strcmp("apbt_only", arg) == 0)
-		disable_apbt_percpu = 0;
-	else if (strcmp("lapic_and_apbt", arg) == 0)
-		disable_apbt_percpu = 1;
-	else {
-		pr_warning("X86 MRST timer option %s not recognised"
-			   " use x86_mrst_timer=apbt_only or lapic_and_apbt\n",
-			   arg);
-		return -EINVAL;
-	}
-	return 0;
-}
-__setup("x86_mrst_timer=", setup_x86_mrst_timer);
-
-/*
  * start count down from 0xffff_ffff. this is done by toggling the enable bit
  * then load initial load count to ~0.
  */
@@ -335,7 +311,7 @@ static int __init apbt_clockevent_register(void)
 	adev->num = smp_processor_id();
 	memcpy(&adev->evt, &apbt_clockevent, sizeof(struct clock_event_device));
 
-	if (disable_apbt_percpu) {
+	if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
 		apbt_clockevent.rating = APBT_CLOCKEVENT_RATING - 100;
 		global_clock_event = &adev->evt;
 		printk(KERN_DEBUG "%s clockevent registered as global\n",
@@ -429,7 +405,8 @@ static int apbt_cpuhp_notify(struct notifier_block *n,
 
 static __init int apbt_late_init(void)
 {
-	if (disable_apbt_percpu || !apb_timer_block_enabled)
+	if (mrst_timer_options == MRST_TIMER_LAPIC_APBT ||
+		!apb_timer_block_enabled)
 		return 0;
 	/* This notifier should be called after workqueue is ready */
 	hotcpu_notifier(apbt_cpuhp_notify, -20);
@@ -450,6 +427,8 @@ static void apbt_set_mode(enum clock_event_mode mode,
 	int timer_num;
 	struct apbt_dev *adev = EVT_TO_APBT_DEV(evt);
 
+	BUG_ON(!apbt_virt_address);
+
 	timer_num = adev->num;
 	pr_debug("%s CPU %d timer %d mode=%d\n",
 		 __func__, first_cpu(*evt->cpumask), timer_num, mode);
@@ -676,7 +655,7 @@ void __init apbt_time_init(void)
 	}
 #ifdef CONFIG_SMP
 	/* kernel cmdline disable apb timer, so we will use lapic timers */
-	if (disable_apbt_percpu) {
+	if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
 		printk(KERN_INFO "apbt: disabled per cpu timer\n");
 		return;
 	}
diff --git a/arch/x86/kernel/mrst.c b/arch/x86/kernel/mrst.c
index 0bca837..13dd3f6 100644
--- a/arch/x86/kernel/mrst.c
+++ b/arch/x86/kernel/mrst.c
@@ -25,6 +25,29 @@
 #include <asm/i8259.h>
 #include <asm/apb_timer.h>
 
+/**
+ * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
+ * cmdline option x86_mrst_timer can be used to override the configuration
+ * to prefer one or the other.
+ * at runtime, there are basically three timer configurations:
+ * 1. per cpu apbt clock only
+ * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only
+ * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast.
+ *
+ * by default (without cmdline option), platform code first detects cpu type
+ * to see if we are on lincroft or penwell, then set up both lapic or apbt
+ * clocks accordingly.
+ * i.e. by default, medfield uses configuration #2, moorestown uses #1.
+ * config #3 is supported but not recommended on medfield.
+ *
+ * rating and feature summary:
+ * lapic (with C3STOP) --------- 100
+ * apbt (always-on) ------------ 110
+ * lapic (always-on,ARAT) ------ 150
+ */
+
+int mrst_timer_options __cpuinitdata;
+
 static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
 static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
 int sfi_mtimer_num;
@@ -167,18 +190,6 @@ int __init sfi_parse_mrtc(struct sfi_table_header *table)
 	return 0;
 }
 
-/*
- * the secondary clock in Moorestown can be APBT or LAPIC clock, default to
- * APBT but cmdline option can also override it.
- */
-static void __cpuinit mrst_setup_secondary_clock(void)
-{
-	/* restore default lapic clock if disabled by cmdline */
-	if (disable_apbt_percpu)
-		return setup_secondary_APIC_clock();
-	apbt_setup_secondary_clock();
-}
-
 static unsigned long __init mrst_calibrate_tsc(void)
 {
 	unsigned long flags, fast_calibrate;
@@ -195,6 +206,26 @@ static unsigned long __init mrst_calibrate_tsc(void)
 
 void __init mrst_time_init(void)
 {
+	switch (mrst_timer_options) {
+	case MRST_TIMER_APBT_ONLY:
+		pr_info("Use APB timer option on Moorestown\n");
+		break;
+	case MRST_TIMER_LAPIC_APBT:
+		pr_info("Use LAPIC and APB timer option on Moorestown\n");
+		x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
+		x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
+		break;
+	default:
+		pr_info("Use default timer option on Moorestown\n");
+		if (mrst_identify_cpu() == MRST_CPU_CHIP_PENWELL) {
+			x86_init.timers.setup_percpu_clockev =
+				setup_boot_APIC_clock;
+			x86_cpuinit.setup_percpu_clockev =
+				setup_secondary_APIC_clock;
+			return;
+		}
+	}
+	/* we need at least one APB timer */
 	sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
 	pre_init_apic_IRQ0();
 	apbt_time_init();
@@ -205,17 +236,6 @@ void __init mrst_rtc_init(void)
 	sfi_table_parse(SFI_SIG_MRTC, NULL, NULL, sfi_parse_mrtc);
 }
 
-/*
- * if we use per cpu apb timer, the bootclock already setup. if we use lapic
- * timer and one apbt timer for broadcast, we need to set up lapic boot clock.
- */
-static void __init mrst_setup_boot_clock(void)
-{
-	pr_info("%s: per cpu apbt flag %d \n", __func__, disable_apbt_percpu);
-	if (disable_apbt_percpu)
-		setup_boot_APIC_clock();
-};
-
 int mrst_identify_cpu(void)
 {
 	u32 mrst_cpu_chip;
@@ -246,11 +266,11 @@ void __init x86_mrst_early_setup(void)
 	x86_init.resources.reserve_resources = x86_init_noop;
 
 	x86_init.timers.timer_init = mrst_time_init;
-	x86_init.timers.setup_percpu_clockev = mrst_setup_boot_clock;
+	x86_init.timers.setup_percpu_clockev = x86_init_noop;
 
 	x86_init.irqs.pre_vector_init = x86_init_noop;
 
-	x86_cpuinit.setup_percpu_clockev = mrst_setup_secondary_clock;
+	x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock;
 
 	x86_platform.calibrate_tsc = mrst_calibrate_tsc;
 	x86_init.pci.init = pci_mrst_init;
@@ -258,3 +278,26 @@ void __init x86_mrst_early_setup(void)
 
 	legacy_pic = &null_legacy_pic;
 }
+
+/*
+ * if user does not want to use per CPU apb timer, just give it a lower rating
+ * than local apic timer and skip the late per cpu timer init.
+ */
+static inline int __init setup_x86_mrst_timer(char *arg)
+{
+	if (!arg)
+		return -EINVAL;
+
+	if (strcmp("apbt_only", arg) == 0)
+		mrst_timer_options = MRST_TIMER_APBT_ONLY;
+	else if (strcmp("lapic_and_apbt", arg) == 0)
+		mrst_timer_options = MRST_TIMER_LAPIC_APBT;
+	else {
+		pr_warning("X86 MRST timer option %s not recognised"
+			   " use x86_mrst_timer=apbt_only or lapic_and_apbt\n",
+			   arg);
+		return -EINVAL;
+	}
+	return 0;
+}
+__setup("x86_mrst_timer=", setup_x86_mrst_timer);
-- 
1.6.3.3

Re: [PATCH 2/2] v4 x86/mrst: add more timer config options

[Thomas Gleixner]

On Tue, 18 May 2010, Jacob Pan wrote:
> Always-on local APIC timer (ARAT) has been introduced to Medfield, along
> with the platform APB timers we have more timer configuration options
> between Moorestown and Medfield.
>  
> +/**

  Do not use kerneldoc /** opener from plain comments. Randy
  complained about that yesterday already

>  void __init mrst_time_init(void)
>  {
> +	switch (mrst_timer_options) {
> +	case MRST_TIMER_APBT_ONLY:
> +		pr_info("Use APB timer option on Moorestown\n");

  Do we really need all this pr_info spew ? /proc/timer_list will tell
  you if you're interested

> +		break;
> +	case MRST_TIMER_LAPIC_APBT:
> +		pr_info("Use LAPIC and APB timer option on Moorestown\n");
> +		x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
> +		x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
> +		break;
> +	default:
> +		pr_info("Use default timer option on Moorestown\n");

  And this printk is completely useless. It'd be way more interesting
  to see which timer gets selected as a default. but see above

> +		if (mrst_identify_cpu() == MRST_CPU_CHIP_PENWELL) {

  Why do you want to pin that on PENWELL and not on ARAT ? If you
  check ARAT, you have coverd all next gen cpus as well.

> +			x86_init.timers.setup_percpu_clockev =
> +				setup_boot_APIC_clock;
> +			x86_cpuinit.setup_percpu_clockev =
> +				setup_secondary_APIC_clock;
> +			return;
> +		}

  You can avoid that line splits by doing:

      	    	if (!has(ARAT))
			break:

		x86_init.timers. ...
		...
		return;

  Way easier to read.

Thanks,

	tglx

Re: [PATCH 2/2] v4 x86/mrst: add more timer config options

[jacob pan]

>>  
>> +/**
>
>  Do not use kerneldoc /** opener from plain comments. Randy
>  complained about that yesterday already
>
I missed randy's comment at the end. sorry. I admit I did not know kernel-doc
before that.

		if (mrst_identify_cpu() == MRST_CPU_CHIP_PENWELL) {
>
>  Why do you want to pin that on PENWELL and not on ARAT ? If you
>  check ARAT, you have coverd all next gen cpus as well.

I did try ARAT first but ARAT is not available at this point. the add-on cpu
features are set later.

Thanks,

Jacob

Re: [PATCH 2/2] v4 x86/mrst: add more timer config options

[Thomas Gleixner]

On Tue, 18 May 2010, jacob pan wrote:

> 
> >>  
> >> +/**
> >
> >  Do not use kerneldoc /** opener from plain comments. Randy
> >  complained about that yesterday already
> >
> I missed randy's comment at the end. sorry. I admit I did not know kernel-doc
> before that.
> 
> 		if (mrst_identify_cpu() == MRST_CPU_CHIP_PENWELL) {
> >
> >  Why do you want to pin that on PENWELL and not on ARAT ? If you
> >  check ARAT, you have coverd all next gen cpus as well.
> 
> I did try ARAT first but ARAT is not available at this point. the add-on cpu
> features are set later.

Hmm, I don't see a reason why we don't to the readout of the extra
features right away. I might be missing something really important
though :) hpa ?????

Thanks,

	tglx

Re: [PATCH 0/2] v3 Moorestown clock related patches

[jacob pan]

This is should be the v4 cover letter instead of v3 shown in the subject line. sorry about that.

Jacob Pan Tue, 18 May 2010 05:02:44 -0700
>Hi,
>Please review the two patches related Moorestown/Medfield clock selection
>logic. tglx has suggested a much cleaner logic in
>http://lkml.org/lkml/2010/5/17/406
>So patch #2 is the implementation of new logic plus small tweaks based on
>testing results.
>I also dropped x86_mask check for Penwell CPU check. It is not needed, CPU
>family and model should be sufficient/accurate to identify Lincroft vs
>Penwell.
>
>*** BLURB HERE ***
>
>Jacob Pan (2):
>  x86/mrst: add cpu type detection
>  x86/mrst: add more timer config options
>
> arch/x86/include/asm/apb_timer.h |    1 -
> arch/x86/include/asm/mrst.h      |   20 +++++++
> arch/x86/kernel/apb_timer.c      |   37 +++----------
> arch/x86/kernel/mrst.c           |  109 ++++++++++++++++++++++++++++++--------
> 4 files changed, 114 insertions(+), 53 deletions(-)
>