From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756520Ab0EYMnn (ORCPT ); Tue, 25 May 2010 08:43:43 -0400 Received: from cavan.codon.org.uk ([93.93.128.6]:41205 "EHLO cavan.codon.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754355Ab0EYMnk (ORCPT ); Tue, 25 May 2010 08:43:40 -0400 Date: Tue, 25 May 2010 13:43:25 +0100 From: Matthew Garrett To: "Yu, Luming" Cc: Len Brown , Philip Langdale , Jeff Garrett , Andi Kleen , Linux Kernel Mailing List , "linux-acpi@vger.kernel.org" , "venki@google.com" Subject: Re: acpi_idle: Very idle Core i7 machine never enters C3 Message-ID: <20100525124325.GC7876@srcf.ucam.org> References: <87y6jkee1b.fsf@basil.nowhere.org> <20100205160900.GA2736@jgarrett.org> <20100426194002.586fbaa5@fido5> <20100427124703.GA16706@jgarrett.org> <20100430174447.GA14889@srcf.ucam.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.18 (2008-05-17) X-SA-Exim-Connect-IP: X-SA-Exim-Mail-From: mjg59@cavan.codon.org.uk X-SA-Exim-Scanned: No (on cavan.codon.org.uk); SAEximRunCond expanded to false Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On the other hand, the relevant section of spec is: "OSPM uses the BM_STS bit to determine the power state to enter when considering a transition to or from the C2/C3 power state. The BM_STS is an optional bit that indicates when bus masters are active. OSPM uses this bit to determine the policy between the C2 and C3 power states: a lot of bus master activity demotes the CPU power state to the C2 (or C1 if C2 is not supported), no bus master activity promotes the CPU power state to the C3 power state. OSPM keeps a running history of the BM_STS bit to determine CPU power state policy." while the description of the bit itself is: "This is the bus master status bit. This bit is set any time a system bus master requests the system bus, and can only be cleared by writing a “1” to this bit position. Notice that this bit reflects bus master activity, not CPU activity (this bit monitors any bus master that can cause an incoherent cache for a processor in the C3 state when the bus master performs a memory transaction)." which implies that as long as you don't have any cache coherency concerns, it's acceptable (if potentially suboptimal) to enter C3 even if the bit is set. -- Matthew Garrett | mjg59@srcf.ucam.org