* [PATCH 02/15] Staging: winbond: Replace C99 comments with C88
2010-05-26 23:39 [PATCH 01/15] Staging: winbond: Fix spacing around brackets and colons Mike Sheldon
@ 2010-05-26 23:39 ` Mike Sheldon
2010-05-26 23:39 ` [PATCH 03/15] Staging: winbond: Fix spacing around brackets, braces, etc Mike Sheldon
` (13 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Mike Sheldon @ 2010-05-26 23:39 UTC (permalink / raw)
To: greg, pavel; +Cc: devel, linux-kernel, Mike Sheldon
This patches mac_structures.h to replace all the C99 style comments (//) with C89 style (/* ... */), as reported by checkpatch.pl.
Signed-off-by: Mike Sheldon <mike@mikeasoft.com>
---
drivers/staging/winbond/mac_structures.h | 18 +++++++++---------
1 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/staging/winbond/mac_structures.h b/drivers/staging/winbond/mac_structures.h
index 84ab290..42dc7a8 100644
--- a/drivers/staging/winbond/mac_structures.h
+++ b/drivers/staging/winbond/mac_structures.h
@@ -98,28 +98,28 @@
#define ELEMENT_ID_CF_PARAMETER_SET 4
#define ELEMENT_ID_TIM 5
#define ELEMENT_ID_IBSS_PARAMETER_SET 6
-// 7~15 reserverd
+/* 7~15 reserverd */
#define ELEMENT_ID_CHALLENGE_TEXT 16
-// 17~31 reserved for challenge text extension
-// 32~255 reserved
-//-- 11G --
+/* 17~31 reserved for challenge text extension */
+/* 32~255 reserved */
+/*-- 11G --*/
#define ELEMENT_ID_ERP_INFORMATION 42
#define ELEMENT_ID_EXTENDED_SUPPORTED_RATES 50
-//-- WPA --
+/*-- WPA --*/
#define ELEMENT_ID_RSN_WPA 221
#ifdef _WPA2_
#define ELEMENT_ID_RSN_WPA2 48
-#endif //endif WPA2
+#endif /*endif WPA2*/
#define WLAN_MAX_PAIRWISE_CIPHER_SUITE_COUNT ((u16) 6)
#define WLAN_MAX_AUTH_KEY_MGT_SUITE_LIST_COUNT ((u16) 2)
-//===================================================================
+/*===================================================================
// Reason Code (Table 18): indicate the reason of DisAssoc, DeAuthen
// length of ReasonCode is 2 Octs.
-//===================================================================
+//===================================================================*/
#define REASON_REASERED 0
#define REASON_UNSPECIDIED 1
#define REASON_PREAUTH_INVALID 2
@@ -430,7 +430,7 @@ struct suite_selector {
};
};
-//-- WPA --
+/*-- WPA --*/
struct RSN_Information_Element {
u8 Element_ID;
u8 Length;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 03/15] Staging: winbond: Fix spacing around brackets, braces, etc.
2010-05-26 23:39 [PATCH 01/15] Staging: winbond: Fix spacing around brackets and colons Mike Sheldon
2010-05-26 23:39 ` [PATCH 02/15] Staging: winbond: Replace C99 comments with C88 Mike Sheldon
@ 2010-05-26 23:39 ` Mike Sheldon
2010-05-26 23:39 ` [PATCH 04/15] Staging: winbond: Replace printk usage with pr_info/pr_err Mike Sheldon
` (12 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Mike Sheldon @ 2010-05-26 23:39 UTC (permalink / raw)
To: greg, pavel; +Cc: devel, linux-kernel, Mike Sheldon
Patches mds.c to correct the spacing around brackets, braces, less than/greater than, equals as reported by checkpatch.pl
Signed-off-by: Mike Sheldon <mike@mikeasoft.com>
---
drivers/staging/winbond/mds.c | 153 ++++++++++++++++++-----------------------
1 files changed, 66 insertions(+), 87 deletions(-)
diff --git a/drivers/staging/winbond/mds.c b/drivers/staging/winbond/mds.c
index e8320a6..477dff4 100644
--- a/drivers/staging/winbond/mds.c
+++ b/drivers/staging/winbond/mds.c
@@ -14,7 +14,7 @@ Mds_initial(struct wbsoft_priv *adapter)
pMds->TxRTSThreshold = DEFAULT_RTSThreshold;
pMds->TxFragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD;
- return hal_get_tx_buffer( &adapter->sHwData, &pMds->pTxBuffer );
+ return hal_get_tx_buffer(&adapter->sHwData, &pMds->pTxBuffer);
}
void
@@ -43,14 +43,13 @@ static void Mds_DurationSet(struct wbsoft_priv *adapter, struct wb35_descriptor
pT01 = (PT01_DESCRIPTOR)(buffer+4);
pNextT00 = (PT00_DESCRIPTOR)(buffer+OffsetSize);
- if( buffer[ DOT_11_DA_OFFSET+8 ] & 0x1 ) /* +8 for USB hdr */
+ if (buffer[DOT_11_DA_OFFSET+8] & 0x1) /* +8 for USB hdr */
boGroupAddr = true;
/******************************************
* Set RTS/CTS mechanism
******************************************/
- if (!boGroupAddr)
- {
+ if (!boGroupAddr) {
/* NOTE : If the protection mode is enabled and the MSDU will be fragmented,
* the tx rates of MPDUs will all be DSSS rates. So it will not use
* CTS-to-self in this case. CTS-To-self will only be used when without
@@ -58,23 +57,19 @@ static void Mds_DurationSet(struct wbsoft_priv *adapter, struct wb35_descriptor
BodyLen = (u16)pT00->T00_frame_length; /* include 802.11 header */
BodyLen += 4; /* CRC */
- if( BodyLen >= CURRENT_RTS_THRESHOLD )
+ if (BodyLen >= CURRENT_RTS_THRESHOLD)
RTS_on = true; /* Using RTS */
- else
- {
- if( pT01->T01_modulation_type ) /* Is using OFDM */
- {
- if( CURRENT_PROTECT_MECHANISM ) /* Is using protect */
+ else {
+ if (pT01->T01_modulation_type) { /* Is using OFDM */
+ if (CURRENT_PROTECT_MECHANISM) /* Is using protect */
CTS_on = true; /* Using CTS */
}
}
}
- if( RTS_on || CTS_on )
- {
- if( pT01->T01_modulation_type) /* Is using OFDM */
- {
- /* CTS duration
+ if (RTS_on || CTS_on) {
+ if (pT01->T01_modulation_type) { /* Is using OFDM */
+ /* CTS duration
* 2 SIFS + DATA transmit time + 1 ACK
* ACK Rate : 24 Mega bps
* ACK frame length = 14 bytes */
@@ -82,44 +77,38 @@ static void Mds_DurationSet(struct wbsoft_priv *adapter, struct wb35_descriptor
2*PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION +
((BodyLen*8 + 22 + Rate*4 - 1)/(Rate*4))*Tsym +
((112 + 22 + 95)/96)*Tsym;
- }
- else /* DSSS */
- {
+ } else { /* DSSS */
/* CTS duration
* 2 SIFS + DATA transmit time + 1 ACK
* Rate : ?? Mega bps
* ACK frame length = 14 bytes */
- if( pT01->T01_plcp_header_length ) /* long preamble */
+ if (pT01->T01_plcp_header_length) /* long preamble */
Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME*2;
else
Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME*2;
- Duration += ( ((BodyLen + 14)*8 + Rate-1) / Rate +
- DEFAULT_SIFSTIME*2 );
+ Duration += (((BodyLen + 14)*8 + Rate-1) / Rate +
+ DEFAULT_SIFSTIME*2);
}
- if( RTS_on )
- {
- if( pT01->T01_modulation_type ) /* Is using OFDM */
- {
+ if (RTS_on) {
+ if (pT01->T01_modulation_type) { /* Is using OFDM */
/* CTS + 1 SIFS + CTS duration
* CTS Rate : 24 Mega bps
* CTS frame length = 14 bytes */
Duration += (DEFAULT_SIFSTIME +
PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION +
((112 + 22 + 95)/96)*Tsym);
- }
- else
- {
+ } else {
/* CTS + 1 SIFS + CTS duration
* CTS Rate : ?? Mega bps
* CTS frame length = 14 bytes */
- if( pT01->T01_plcp_header_length ) /* long preamble */
+ if (pT01->T01_plcp_header_length) /* long preamble */
Duration += LONG_PREAMBLE_PLUS_PLCPHEADER_TIME;
else
Duration += SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME;
- Duration += ( ((112 + Rate-1) / Rate) + DEFAULT_SIFSTIME );
+ Duration += (((112 + Rate-1) / Rate) + DEFAULT_SIFSTIME);
}
}
@@ -132,17 +121,14 @@ static void Mds_DurationSet(struct wbsoft_priv *adapter, struct wb35_descriptor
/******************************************
* Fill the more fragment descriptor
******************************************/
- if( boGroupAddr )
+ if (boGroupAddr)
Duration = 0;
- else
- {
- for( i=pDes->FragmentCount-1; i>0; i-- )
- {
+ else {
+ for (i = pDes->FragmentCount-1; i > 0; i--) {
NextBodyLen = (u16)pNextT00->T00_frame_length;
NextBodyLen += 4; /* CRC */
- if( pT01->T01_modulation_type )
- {
+ if (pT01->T01_modulation_type) {
/* OFDM
* data transmit time + 3 SIFS + 2 ACK
* Rate : ??Mega bps
@@ -151,28 +137,26 @@ static void Mds_DurationSet(struct wbsoft_priv *adapter, struct wb35_descriptor
Duration += (((NextBodyLen*8 + 22 + Rate*4 - 1)/(Rate*4)) * Tsym +
(((2*14)*8 + 22 + 95)/96)*Tsym +
DEFAULT_SIFSTIME*3);
- }
- else
- {
+ } else {
/* DSSS
* data transmit time + 2 ACK + 3 SIFS
* Rate : ??Mega bps
* ACK frame length = 14 bytes
* TODO : */
- if( pT01->T01_plcp_header_length ) /* long preamble */
+ if (pT01->T01_plcp_header_length) /* long preamble */
Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME*3;
else
Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME*3;
- Duration += ( ((NextBodyLen + (2*14))*8 + Rate-1) / Rate +
- DEFAULT_SIFSTIME*3 );
+ Duration += (((NextBodyLen + (2*14))*8 + Rate-1) / Rate +
+ DEFAULT_SIFSTIME*3);
}
((u16 *)buffer)[5] = cpu_to_le16(Duration); /* 4 USHOR for skip 8B USB, 2USHORT=FC + Duration */
/* ----20061009 add by anson's endian */
pNextT00->value = cpu_to_le32(pNextT00->value);
- pT01->value = cpu_to_le32( pT01->value );
+ pT01->value = cpu_to_le32(pT01->value);
/* ----end 20061009 add by anson's endian */
buffer += OffsetSize;
@@ -184,28 +168,25 @@ static void Mds_DurationSet(struct wbsoft_priv *adapter, struct wb35_descriptor
/*******************************************
* Fill the last fragment descriptor
*******************************************/
- if( pT01->T01_modulation_type )
- {
+ if (pT01->T01_modulation_type) {
/* OFDM
* 1 SIFS + 1 ACK
* Rate : 24 Mega bps
* ACK frame length = 14 bytes */
Duration = PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION;
/* The Tx rate of ACK use 24M */
- Duration += (((112 + 22 + 95)/96)*Tsym + DEFAULT_SIFSTIME );
- }
- else
- {
+ Duration += (((112 + 22 + 95)/96)*Tsym + DEFAULT_SIFSTIME);
+ } else {
/* DSSS
* 1 ACK + 1 SIFS
* Rate : ?? Mega bps
* ACK frame length = 14 bytes(112 bits) */
- if( pT01->T01_plcp_header_length ) /* long preamble */
+ if (pT01->T01_plcp_header_length) /* long preamble */
Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME;
else
Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME;
- Duration += ( (112 + Rate-1)/Rate + DEFAULT_SIFSTIME );
+ Duration += ((112 + Rate-1)/Rate + DEFAULT_SIFSTIME);
}
}
@@ -247,10 +228,10 @@ static u16 Mds_BodyCopy(struct wbsoft_priv *adapter, struct wb35_descriptor *pDe
SizeLeft -= CopySize;
/* 1 Byte operation */
- pctmp = (u8 *)( buffer + 8 + DOT_11_SEQUENCE_OFFSET );
+ pctmp = (u8 *)(buffer + 8 + DOT_11_SEQUENCE_OFFSET);
*pctmp &= 0xf0;
*pctmp |= FragmentCount; /* 931130.5.m */
- if( !FragmentCount )
+ if (!FragmentCount)
pT00->T00_first_mpdu = 1;
buffer += 32; /* 8B usb + 24B 802.11 header */
@@ -286,15 +267,13 @@ static u16 Mds_BodyCopy(struct wbsoft_priv *adapter, struct wb35_descriptor *pDe
/* 931130.5.n */
if (pMds->MicAdd) {
if (!SizeLeft) {
- pMds->MicWriteAddress[ pMds->MicWriteIndex ] = buffer - pMds->MicAdd;
- pMds->MicWriteSize[ pMds->MicWriteIndex ] = pMds->MicAdd;
+ pMds->MicWriteAddress[pMds->MicWriteIndex] = buffer - pMds->MicAdd;
+ pMds->MicWriteSize[pMds->MicWriteIndex] = pMds->MicAdd;
pMds->MicAdd = 0;
- }
- else if( SizeLeft < 8 ) /* 931130.5.p */
- {
+ } else if (SizeLeft < 8) { /* 931130.5.p */
pMds->MicAdd = SizeLeft;
- pMds->MicWriteAddress[ pMds->MicWriteIndex ] = buffer - ( 8 - SizeLeft );
- pMds->MicWriteSize[ pMds->MicWriteIndex ] = 8 - SizeLeft;
+ pMds->MicWriteAddress[pMds->MicWriteIndex] = buffer - (8 - SizeLeft);
+ pMds->MicWriteSize[pMds->MicWriteIndex] = 8 - SizeLeft;
pMds->MicWriteIndex++;
}
}
@@ -302,7 +281,7 @@ static u16 Mds_BodyCopy(struct wbsoft_priv *adapter, struct wb35_descriptor *pDe
/* Does it need to generate the new header for next mpdu? */
if (SizeLeft) {
buffer = TargetBuffer + Size; /* Get the next 4n start address */
- memcpy( buffer, TargetBuffer, 32 ); /* Copy 8B USB +24B 802.11 */
+ memcpy(buffer, TargetBuffer, 32); /* Copy 8B USB +24B 802.11 */
pT00 = (PT00_DESCRIPTOR)buffer;
pT00->T00_first_mpdu = 0;
}
@@ -350,7 +329,7 @@ static void Mds_HeaderCopy(struct wbsoft_priv *adapter, struct wb35_descriptor *
FragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD; /* Do not fragment */
/* Copy full data, the 1'st buffer contain all the data 931130.5.j */
- memcpy( TargetBuffer, src_buffer, DOT_11_MAC_HEADER_SIZE ); /* Copy header */
+ memcpy(TargetBuffer, src_buffer, DOT_11_MAC_HEADER_SIZE); /* Copy header */
pDes->buffer_address[0] = src_buffer + DOT_11_MAC_HEADER_SIZE;
pDes->buffer_total_size -= DOT_11_MAC_HEADER_SIZE;
pDes->buffer_size[0] = pDes->buffer_total_size;
@@ -377,26 +356,26 @@ static void Mds_HeaderCopy(struct wbsoft_priv *adapter, struct wb35_descriptor *
pT01->T01_modulation_type = (ctmp1%3) ? 0 : 1;
- for( i=0; i<2; i++ ) {
- if( i == 1 )
+ for (i = 0; i < 2; i++) {
+ if (i == 1)
ctmp1 = ctmpf;
pMds->TxRate[pDes->Descriptor_ID][i] = ctmp1; /* backup the ta rate and fall back rate */
- if( ctmp1 == 108) ctmp2 = 7;
- else if( ctmp1 == 96 ) ctmp2 = 6; /* Rate convert for USB */
- else if( ctmp1 == 72 ) ctmp2 = 5;
- else if( ctmp1 == 48 ) ctmp2 = 4;
- else if( ctmp1 == 36 ) ctmp2 = 3;
- else if( ctmp1 == 24 ) ctmp2 = 2;
- else if( ctmp1 == 18 ) ctmp2 = 1;
- else if( ctmp1 == 12 ) ctmp2 = 0;
- else if( ctmp1 == 22 ) ctmp2 = 3;
- else if( ctmp1 == 11 ) ctmp2 = 2;
- else if( ctmp1 == 4 ) ctmp2 = 1;
+ if (ctmp1 == 108) ctmp2 = 7;
+ else if (ctmp1 == 96) ctmp2 = 6; /* Rate convert for USB */
+ else if (ctmp1 == 72) ctmp2 = 5;
+ else if (ctmp1 == 48) ctmp2 = 4;
+ else if (ctmp1 == 36) ctmp2 = 3;
+ else if (ctmp1 == 24) ctmp2 = 2;
+ else if (ctmp1 == 18) ctmp2 = 1;
+ else if (ctmp1 == 12) ctmp2 = 0;
+ else if (ctmp1 == 22) ctmp2 = 3;
+ else if (ctmp1 == 11) ctmp2 = 2;
+ else if (ctmp1 == 4) ctmp2 = 1;
else ctmp2 = 0; /* if( ctmp1 == 2 ) or default */
- if( i == 0 )
+ if (i == 0)
pT01->T01_transmit_rate = ctmp2;
else
pT01->T01_fall_back_rate = ctmp2;
@@ -474,14 +453,14 @@ Mds_Tx(struct wbsoft_priv *adapter)
TxDesIndex = pMds->TxDesIndex; /* Get the current ID */
pTxDes->Descriptor_ID = TxDesIndex;
- pMds->TxDesFrom[ TxDesIndex ] = 2; /* Storing the information of source comming from */
+ pMds->TxDesFrom[TxDesIndex] = 2; /* Storing the information of source comming from */
pMds->TxDesIndex++;
pMds->TxDesIndex %= MAX_USB_TX_DESCRIPTOR;
- MLME_GetNextPacket( adapter, pTxDes );
+ MLME_GetNextPacket(adapter, pTxDes);
/* Copy header. 8byte USB + 24byte 802.11Hdr. Set TxRate, Preamble type */
- Mds_HeaderCopy( adapter, pTxDes, XmitBufAddress );
+ Mds_HeaderCopy(adapter, pTxDes, XmitBufAddress);
/* For speed up Key setting */
if (pTxDes->EapFix) {
@@ -502,7 +481,7 @@ Mds_Tx(struct wbsoft_priv *adapter)
XmitBufAddress += CurrentSize;
#ifdef _IBSS_BEACON_SEQ_STICK_
- if ((XmitBufAddress[ DOT_11_DA_OFFSET+8 ] & 0xfc) != MAC_SUBTYPE_MNGMNT_PROBE_REQUEST) /* +8 for USB hdr */
+ if ((XmitBufAddress[DOT_11_DA_OFFSET+8] & 0xfc) != MAC_SUBTYPE_MNGMNT_PROBE_REQUEST) /* +8 for USB hdr */
#endif
pMds->TxToggle = true;
@@ -520,7 +499,7 @@ Mds_Tx(struct wbsoft_priv *adapter)
/* Move to the next one, if necessary */
if (BufferFilled) {
/* size setting */
- pMds->TxBufferSize[ FillIndex ] = XmitBufSize;
+ pMds->TxBufferSize[FillIndex] = XmitBufSize;
/* 20060928 set Tx count */
pMds->TxCountInBuffer[FillIndex] = FillCount;
@@ -537,7 +516,7 @@ Mds_Tx(struct wbsoft_priv *adapter)
if (!PacketSize) /* No more pk for transmitting */
break;
- } while(true);
+ } while (true);
/*
* Start to send by lower module
@@ -563,7 +542,7 @@ Mds_SendComplete(struct wbsoft_priv *adapter, PT02_DESCRIPTOR pT02)
if (pT02->T02_IsLastMpdu) {
/* TODO: DTO -- get the retry count and fragment count */
/* Tx rate */
- TxRate = pMds->TxRate[ PacketId ][ 0 ];
+ TxRate = pMds->TxRate[PacketId][0];
RetryCount = (u8)pT02->T02_MPDU_Cnt;
if (pT02->value & FLAG_ERROR_TX_MASK) {
SendOK = false;
@@ -572,7 +551,7 @@ Mds_SendComplete(struct wbsoft_priv *adapter, PT02_DESCRIPTOR pT02)
/* retry error */
pHwData->dto_tx_retry_count += (RetryCount+1);
/* [for tx debug] */
- if (RetryCount<7)
+ if (RetryCount < 7)
pHwData->tx_retry_count[RetryCount] += RetryCount;
else
pHwData->tx_retry_count[7] += RetryCount;
@@ -597,7 +576,7 @@ Mds_SendComplete(struct wbsoft_priv *adapter, PT02_DESCRIPTOR pT02)
}
/* Clear send result buffer */
- pMds->TxResult[ PacketId ] = 0;
+ pMds->TxResult[PacketId] = 0;
} else
- pMds->TxResult[ PacketId ] |= ((u16)(pT02->value & 0x0ffff));
+ pMds->TxResult[PacketId] |= ((u16)(pT02->value & 0x0ffff));
}
--
1.7.0.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 04/15] Staging: winbond: Replace printk usage with pr_info/pr_err
2010-05-26 23:39 [PATCH 01/15] Staging: winbond: Fix spacing around brackets and colons Mike Sheldon
2010-05-26 23:39 ` [PATCH 02/15] Staging: winbond: Replace C99 comments with C88 Mike Sheldon
2010-05-26 23:39 ` [PATCH 03/15] Staging: winbond: Fix spacing around brackets, braces, etc Mike Sheldon
@ 2010-05-26 23:39 ` Mike Sheldon
2010-05-26 23:39 ` [PATCH 05/15] Staging: winbond: Fix spacing around brackets, braces, etc Mike Sheldon
` (11 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Mike Sheldon @ 2010-05-26 23:39 UTC (permalink / raw)
To: greg, pavel; +Cc: devel, linux-kernel, Mike Sheldon
Patches mds.c to replace printk usage (missing KERN_ levels) with appropriate pr_info and pr_err calls.
Signed-off-by: Mike Sheldon <mike@mikeasoft.com>
---
drivers/staging/winbond/mds.c | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/staging/winbond/mds.c b/drivers/staging/winbond/mds.c
index 477dff4..c4b48c8 100644
--- a/drivers/staging/winbond/mds.c
+++ b/drivers/staging/winbond/mds.c
@@ -351,7 +351,7 @@ static void Mds_HeaderCopy(struct wbsoft_priv *adapter, struct wb35_descriptor *
pDes->TxRate = ctmp1;
#ifdef _PE_TX_DUMP_
- printk("Tx rate =%x\n", ctmp1);
+ pr_info("Tx rate = %x\n", ctmp1);
#endif
pT01->T01_modulation_type = (ctmp1%3) ? 0 : 1;
@@ -419,7 +419,7 @@ Mds_Tx(struct wbsoft_priv *adapter)
FillIndex = pMds->TxFillIndex;
if (pMds->TxOwner[FillIndex]) { /* Is owned by software 0:Yes 1:No */
#ifdef _PE_TX_DUMP_
- printk("[Mds_Tx] Tx Owner is H/W.\n");
+ pr_info("[Mds_Tx] Tx Owner is H/W.\n");
#endif
break;
}
@@ -438,7 +438,7 @@ Mds_Tx(struct wbsoft_priv *adapter)
FragmentCount = PacketSize/FragmentThreshold + 1;
stmp = PacketSize + FragmentCount*32 + 8; /* 931130.5.c 8:MIC */
if ((XmitBufSize + stmp) >= MAX_USB_TX_BUFFER) {
- printk("[Mds_Tx] Excess max tx buffer.\n");
+ pr_err("[Mds_Tx] Excess max tx buffer.\n");
break; /* buffer is not enough */
}
@@ -465,7 +465,7 @@ Mds_Tx(struct wbsoft_priv *adapter)
/* For speed up Key setting */
if (pTxDes->EapFix) {
#ifdef _PE_TX_DUMP_
- printk("35: EPA 4th frame detected. Size = %d\n", PacketSize);
+ pr_info("35: EPA 4th frame detected. Size = %d\n", PacketSize);
#endif
pHwData->IsKeyPreSet = 1;
}
@@ -556,7 +556,7 @@ Mds_SendComplete(struct wbsoft_priv *adapter, PT02_DESCRIPTOR pT02)
else
pHwData->tx_retry_count[7] += RetryCount;
#ifdef _PE_STATE_DUMP_
- printk("dto_tx_retry_count =%d\n", pHwData->dto_tx_retry_count);
+ pr_info("dto_tx_retry_count = %d\n", pHwData->dto_tx_retry_count);
#endif
MTO_SetTxCount(adapter, TxRate, RetryCount);
}
--
1.7.0.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 05/15] Staging: winbond: Fix spacing around brackets, braces, etc.
2010-05-26 23:39 [PATCH 01/15] Staging: winbond: Fix spacing around brackets and colons Mike Sheldon
` (2 preceding siblings ...)
2010-05-26 23:39 ` [PATCH 04/15] Staging: winbond: Replace printk usage with pr_info/pr_err Mike Sheldon
@ 2010-05-26 23:39 ` Mike Sheldon
2010-05-26 23:39 ` [PATCH 06/15] Staging: winbond: Replace C99 comments with C88 Mike Sheldon
` (10 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Mike Sheldon @ 2010-05-26 23:39 UTC (permalink / raw)
To: greg, pavel; +Cc: devel, linux-kernel, Mike Sheldon
Patches phy_calibration.c to correct the spacing around brackets, braces, less than/greater than, equals and remove some extraneous braces as reported by checkpatch.pl
Signed-off-by: Mike Sheldon <mike@mikeasoft.com>
---
drivers/staging/winbond/phy_calibration.c | 471 ++++++++++-------------------
1 files changed, 159 insertions(+), 312 deletions(-)
diff --git a/drivers/staging/winbond/phy_calibration.c b/drivers/staging/winbond/phy_calibration.c
index 7893586..c007c06 100644
--- a/drivers/staging/winbond/phy_calibration.c
+++ b/drivers/staging/winbond/phy_calibration.c
@@ -25,12 +25,11 @@
#define FIXED(X) ((s32)((X) * 32768.0))
#define DEG2RAD(X) 0.017453 * (X)
-static const s32 Angles[] =
-{
- FIXED(DEG2RAD(45.0)), FIXED(DEG2RAD(26.565)), FIXED(DEG2RAD(14.0362)),
- FIXED(DEG2RAD(7.12502)), FIXED(DEG2RAD(3.57633)), FIXED(DEG2RAD(1.78991)),
- FIXED(DEG2RAD(0.895174)),FIXED(DEG2RAD(0.447614)),FIXED(DEG2RAD(0.223811)),
- FIXED(DEG2RAD(0.111906)),FIXED(DEG2RAD(0.055953)),FIXED(DEG2RAD(0.027977))
+static const s32 Angles[] = {
+ FIXED(DEG2RAD(45.0)), FIXED(DEG2RAD(26.565)), FIXED(DEG2RAD(14.0362)),
+ FIXED(DEG2RAD(7.12502)), FIXED(DEG2RAD(3.57633)), FIXED(DEG2RAD(1.78991)),
+ FIXED(DEG2RAD(0.895174)), FIXED(DEG2RAD(0.447614)), FIXED(DEG2RAD(0.223811)),
+ FIXED(DEG2RAD(0.111906)), FIXED(DEG2RAD(0.055953)), FIXED(DEG2RAD(0.027977))
};
/****************** LOCAL FUNCTION DECLARATION SECTION **********************/
@@ -46,9 +45,7 @@ s32 _s13_to_s32(u32 data)
val = (data & 0x0FFF);
if ((data & BIT(12)) != 0)
- {
val |= 0xFFFFF000;
- }
return ((s32) val);
}
@@ -58,13 +55,9 @@ u32 _s32_to_s13(s32 data)
u32 val;
if (data > 4095)
- {
data = 4095;
- }
else if (data < -4096)
- {
data = -4096;
- }
val = data & 0x1FFF;
@@ -79,9 +72,7 @@ s32 _s4_to_s32(u32 data)
val = (data & 0x0007);
if ((data & BIT(3)) != 0)
- {
val |= 0xFFFFFFF8;
- }
return val;
}
@@ -91,13 +82,9 @@ u32 _s32_to_s4(s32 data)
u32 val;
if (data > 7)
- {
data = 7;
- }
else if (data < -8)
- {
data = -8;
- }
val = data & 0x000F;
@@ -112,9 +99,7 @@ s32 _s5_to_s32(u32 data)
val = (data & 0x000F);
if ((data & BIT(4)) != 0)
- {
val |= 0xFFFFFFF0;
- }
return val;
}
@@ -124,13 +109,9 @@ u32 _s32_to_s5(s32 data)
u32 val;
if (data > 15)
- {
data = 15;
- }
else if (data < -16)
- {
data = -16;
- }
val = data & 0x001F;
@@ -145,9 +126,7 @@ s32 _s6_to_s32(u32 data)
val = (data & 0x001F);
if ((data & BIT(5)) != 0)
- {
val |= 0xFFFFFFE0;
- }
return val;
}
@@ -157,13 +136,9 @@ u32 _s32_to_s6(s32 data)
u32 val;
if (data > 31)
- {
data = 31;
- }
else if (data < -32)
- {
data = -32;
- }
val = data & 0x003F;
@@ -178,9 +153,7 @@ s32 _s9_to_s32(u32 data)
val = data & 0x00FF;
if ((data & BIT(8)) != 0)
- {
val |= 0xFFFFFF00;
- }
return val;
}
@@ -190,13 +163,9 @@ u32 _s32_to_s9(s32 data)
u32 val;
if (data > 255)
- {
data = 255;
- }
else if (data < -256)
- {
data = -256;
- }
val = data & 0x01FF;
@@ -207,13 +176,9 @@ u32 _s32_to_s9(s32 data)
s32 _floor(s32 n)
{
if (n > 0)
- {
n += 5;
- }
else
- {
n -= 5;
- }
return (n/10);
}
@@ -240,8 +205,7 @@ u32 _sqrt(u32 sqsum)
next = g4;
step = 0;
seed = 0;
- while (((seed+1)*(step+1)) <= next)
- {
+ while (((seed+1)*(step+1)) <= next) {
step++;
seed++;
}
@@ -251,8 +215,7 @@ u32 _sqrt(u32 sqsum)
step = 0;
seed = 2 * seed * 10;
- while (((seed+1)*(step+1)) <= next)
- {
+ while (((seed+1)*(step+1)) <= next ) {
step++;
seed++;
}
@@ -261,8 +224,7 @@ u32 _sqrt(u32 sqsum)
next = (next - seed * step) * 100 + g2;
seed = (seed + step) * 10;
step = 0;
- while (((seed+1)*(step+1)) <= next)
- {
+ while (((seed+1)*(step+1)) <= next) {
step++;
seed++;
}
@@ -272,8 +234,7 @@ u32 _sqrt(u32 sqsum)
seed = (seed + step) * 10;
step = 0;
- while (((seed+1)*(step+1)) <= next)
- {
+ while (((seed+1)*(step+1)) <= next) {
step++;
seed++;
}
@@ -283,8 +244,7 @@ u32 _sqrt(u32 sqsum)
seed = (seed + step) * 10;
step = 0;
- while (((seed+1)*(step+1)) <= next)
- {
+ while (((seed+1)*(step+1)) <= next) {
step++;
seed++;
}
@@ -300,38 +260,31 @@ void _sin_cos(s32 angle, s32 *sin, s32 *cos)
s32 X, Y, TargetAngle, CurrAngle;
unsigned Step;
- X=FIXED(AG_CONST); // AG_CONST * cos(0)
- Y=0; // AG_CONST * sin(0)
- TargetAngle=abs(angle);
- CurrAngle=0;
+ X = FIXED(AG_CONST); // AG_CONST * cos(0)
+ Y = 0; // AG_CONST * sin(0)
+ TargetAngle = abs(angle);
+ CurrAngle = 0;
- for (Step=0; Step < 12; Step++)
- {
+ for (Step = 0; Step < 12; Step++) {
s32 NewX;
- if(TargetAngle > CurrAngle)
- {
- NewX=X - (Y >> Step);
- Y=(X >> Step) + Y;
- X=NewX;
+ if (TargetAngle > CurrAngle) {
+ NewX = X - (Y >> Step);
+ Y = (X >> Step) + Y;
+ X = NewX;
CurrAngle += Angles[Step];
- }
- else
- {
- NewX=X + (Y >> Step);
- Y=-(X >> Step) + Y;
- X=NewX;
+ } else {
+ NewX = X + (Y >> Step);
+ Y = -(X >> Step) + Y;
+ X = NewX;
CurrAngle -= Angles[Step];
}
}
- if (angle > 0)
- {
+ if (angle > 0) {
*cos = X;
*sin = Y;
- }
- else
- {
+ } else {
*cos = X;
*sin = -Y;
}
@@ -343,7 +296,7 @@ static unsigned char hal_get_dxx_reg(struct hw_data *pHwData, u16 number, u32 *
number += 0x1000;
return Wb35Reg_ReadSync(pHwData, number, pValue);
}
-#define hw_get_dxx_reg( _A, _B, _C ) hal_get_dxx_reg( _A, _B, (u32 *)_C )
+#define hw_get_dxx_reg(_A, _B, _C) hal_get_dxx_reg(_A, _B, (u32 *)_C)
static unsigned char hal_set_dxx_reg(struct hw_data *pHwData, u16 number, u32 value)
{
@@ -354,7 +307,7 @@ static unsigned char hal_set_dxx_reg(struct hw_data *pHwData, u16 number, u32 va
ret = Wb35Reg_WriteSync(pHwData, number, value);
return ret;
}
-#define hw_set_dxx_reg( _A, _B, _C ) hal_set_dxx_reg( _A, _B, (u32)_C )
+#define hw_set_dxx_reg(_A, _B, _C) hal_set_dxx_reg(_A, _B, (u32)_C)
void _reset_rx_cal(struct hw_data *phw_data)
@@ -364,13 +317,9 @@ void _reset_rx_cal(struct hw_data *phw_data)
hw_get_dxx_reg(phw_data, 0x54, &val);
if (phw_data->revision == 0x2002) // 1st-cut
- {
val &= 0xFFFF0000;
- }
else // 2nd-cut
- {
val &= 0x000003FF;
- }
hw_set_dxx_reg(phw_data, 0x54, val);
}
@@ -393,21 +342,15 @@ void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequen
phy_init_rf(phw_data);
// set calibration channel
- if( (RF_WB_242 == phw_data->phy_type) ||
- (RF_WB_242_1 == phw_data->phy_type) ) // 20060619.5 Add
- {
- if ((frequency >= 2412) && (frequency <= 2484))
- {
+ if ((RF_WB_242 == phw_data->phy_type) ||
+ (RF_WB_242_1 == phw_data->phy_type)) { // 20060619.5 Add
+ if ((frequency >= 2412) && (frequency <= 2484)) {
// w89rf242 change frequency to 2390Mhz
PHY_DEBUG(("[CAL] W89RF242/11G/Channel=2390Mhz\n"));
phy_set_rf_data(phw_data, 3, (3<<24)|0x025586);
}
- }
- else
- {
-
- }
+ }
// reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel
hw_get_dxx_reg(phw_data, 0x5C, &val);
@@ -542,8 +485,7 @@ void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data)
hw_get_dxx_reg(phw_data, 0x5C, ®_dc_cancel);
PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel));
- for (loop = 0; loop < LOOP_TIMES; loop++)
- {
+ for (loop = 0; loop < LOOP_TIMES; loop++) {
PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop));
// c.
@@ -579,15 +521,10 @@ void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data)
// e. Calculate the correct DC offset cancellation value for I
if (mag_0 != mag_1)
- {
fix_cancel_dc_i = (mag_0*10000) / (mag_0*10000 - mag_1*10000);
- }
- else
- {
+ else {
if (mag_0 == mag_1)
- {
PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n"));
- }
fix_cancel_dc_i = 0;
}
@@ -596,12 +533,10 @@ void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data)
fix_cancel_dc_i, _s32_to_s5(fix_cancel_dc_i)));
if ((abs(mag_1-mag_0)*6) > mag_0)
- {
break;
- }
}
- if ( loop >= 19 )
+ if (loop >= 19)
fix_cancel_dc_i = 0;
reg_dc_cancel &= ~(0x03FF);
@@ -667,8 +602,7 @@ void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data)
hw_get_dxx_reg(phw_data, 0x5C, ®_dc_cancel);
PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel));
- for (loop = 0; loop < LOOP_TIMES; loop++)
- {
+ for (loop = 0; loop < LOOP_TIMES; loop++) {
PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop));
// b.
@@ -703,16 +637,11 @@ void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data)
mag_1, iqcal_image_i, iqcal_image_q));
// d. Calculate the correct DC offset cancellation value for I
- if (mag_0 != mag_1)
- {
+ if (mag_0 != mag_1) {
fix_cancel_dc_q = (mag_0*10000) / (mag_0*10000 - mag_1*10000);
- }
- else
- {
+ } else {
if (mag_0 == mag_1)
- {
PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n"));
- }
fix_cancel_dc_q = 0;
}
@@ -720,13 +649,11 @@ void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data)
PHY_DEBUG(("[CAL] ** fix_cancel_dc_q = %d (0x%04X)\n",
fix_cancel_dc_q, _s32_to_s5(fix_cancel_dc_q)));
- if ((abs(mag_1-mag_0)*6) > mag_0)
- {
+ if ((abs(mag_1-mag_0)*6) > mag_0)
break;
- }
}
- if ( loop >= 19 )
+ if (loop >= 19)
fix_cancel_dc_q = 0;
reg_dc_cancel &= ~(0x001F);
@@ -765,7 +692,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
s32 temp1, temp2;
u32 val;
u16 loop;
- s32 iqcal_tone_i_avg,iqcal_tone_q_avg;
+ s32 iqcal_tone_i_avg, iqcal_tone_q_avg;
u8 verify_count;
int capture_time;
@@ -780,16 +707,14 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
loop = LOOP_TIMES;
- while (loop > 0)
- {
+ while (loop > 0) {
PHY_DEBUG(("[CAL] [%d.] <_tx_iq_calibration_loop>\n", (LOOP_TIMES-loop+1)));
- iqcal_tone_i_avg=0;
- iqcal_tone_q_avg=0;
- if( !hw_set_dxx_reg(phw_data, 0x3C, 0x00) ) // 20060718.1 modify
+ iqcal_tone_i_avg = 0;
+ iqcal_tone_q_avg = 0;
+ if (!hw_set_dxx_reg(phw_data, 0x3C, 0x00)) // 20060718.1 modify
return 0;
- for(capture_time=0;capture_time<10;capture_time++)
- {
+ for (capture_time = 0; capture_time < 10; capture_time++) {
// a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to
// enable "IQ alibration Mode II"
reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
@@ -835,14 +760,11 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13);
PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n",
iqcal_tone_i, iqcal_tone_q));
- if( capture_time == 0)
- {
+ if (capture_time == 0)
continue;
- }
- else
- {
- iqcal_tone_i_avg=( iqcal_tone_i_avg*(capture_time-1) +iqcal_tone_i)/capture_time;
- iqcal_tone_q_avg=( iqcal_tone_q_avg*(capture_time-1) +iqcal_tone_q)/capture_time;
+ else {
+ iqcal_tone_i_avg = (iqcal_tone_i_avg*(capture_time-1) + iqcal_tone_i)/capture_time;
+ iqcal_tone_q_avg = (iqcal_tone_q_avg*(capture_time-1) + iqcal_tone_q)/capture_time;
}
}
@@ -860,8 +782,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
// f.
divisor = ((iq_mag_0_tx * iq_mag_0_tx * 2)/1024 - rot_i_b) * 2;
- if (divisor == 0)
- {
+ if (divisor == 0) {
PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> ERROR *******\n"));
PHY_DEBUG(("[CAL] ** divisor=0 to calculate EPS and THETA !!\n"));
PHY_DEBUG(("[CAL] ******************************************\n"));
@@ -878,16 +799,14 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
//if ((abs(a_2) < 150) && (abs(b_2) < 100))
//if ((abs(a_2) < 200) && (abs(b_2) < 200))
- if ((abs(a_2) < a_2_threshold) && (abs(b_2) < b_2_threshold))
- {
+ if ((abs(a_2) < a_2_threshold) && (abs(b_2) < b_2_threshold)) {
verify_count++;
PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n"));
PHY_DEBUG(("[CAL] ** VERIFY OK # %d !!\n", verify_count));
PHY_DEBUG(("[CAL] ******************************************\n"));
- if (verify_count > 2)
- {
+ if (verify_count > 2) {
PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n"));
PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION (EPS,THETA) OK !!\n"));
PHY_DEBUG(("[CAL] **************************************\n"));
@@ -895,9 +814,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
}
continue;
- }
- else
- {
+ } else {
verify_count = 0;
}
@@ -906,8 +823,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
PHY_DEBUG(("[CAL] ** sin(b/2)=%d, cos(b/2)=%d\n", sin_b, cos_b));
PHY_DEBUG(("[CAL] ** sin(b)=%d, cos(b)=%d\n", sin_2b, cos_2b));
- if (cos_2b == 0)
- {
+ if (cos_2b == 0) {
PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> ERROR *******\n"));
PHY_DEBUG(("[CAL] ** cos(b)=0 !!\n"));
PHY_DEBUG(("[CAL] ******************************************\n"));
@@ -919,13 +835,9 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
//temp2 = (41943040/cos_2b)*sin_b*(-1);
if (phw_data->revision == 0x2002) // 1st-cut
- {
temp2 = (41943040/cos_2b)*sin_b*(-1);
- }
else // 2nd-cut
- {
temp2 = (41943040*4/cos_2b)*sin_b*(-1);
- }
tx_cal_flt_b[0] = _floor(temp1/(32768+a_2));
tx_cal_flt_b[1] = _floor(temp2/(32768+a_2));
@@ -957,17 +869,14 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
//}
// g.
- if (phw_data->revision == 0x2002) // 1st-cut
- {
+ if (phw_data->revision == 0x2002) { // 1st-cut
hw_get_dxx_reg(phw_data, 0x54, &val);
PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
tx_cal_reg[0] = _s4_to_s32((val & 0xF0000000) >> 28);
tx_cal_reg[1] = _s4_to_s32((val & 0x0F000000) >> 24);
tx_cal_reg[2] = _s4_to_s32((val & 0x00F00000) >> 20);
tx_cal_reg[3] = _s4_to_s32((val & 0x000F0000) >> 16);
- }
- else // 2nd-cut
- {
+ } else { // 2nd-cut
hw_get_dxx_reg(phw_data, 0x3C, &val);
PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val));
tx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
@@ -982,22 +891,17 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
PHY_DEBUG(("[CAL] tx_cal_reg[2] = %d\n", tx_cal_reg[2]));
PHY_DEBUG(("[CAL] tx_cal_reg[3] = %d\n", tx_cal_reg[3]));
- if (phw_data->revision == 0x2002) // 1st-cut
- {
- if (((tx_cal_reg[0]==7) || (tx_cal_reg[0]==(-8))) &&
- ((tx_cal_reg[3]==7) || (tx_cal_reg[3]==(-8))))
- {
+ if (phw_data->revision == 0x2002) { // 1st-cut
+ if (((tx_cal_reg[0] == 7) || (tx_cal_reg[0] == (-8))) &&
+ ((tx_cal_reg[3] == 7) || (tx_cal_reg[3] == (-8)))) {
PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n"));
PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION SATUATION !!\n"));
PHY_DEBUG(("[CAL] **************************************\n"));
break;
}
- }
- else // 2nd-cut
- {
- if (((tx_cal_reg[0]==31) || (tx_cal_reg[0]==(-32))) &&
- ((tx_cal_reg[3]==31) || (tx_cal_reg[3]==(-32))))
- {
+ } else { // 2nd-cut
+ if (((tx_cal_reg[0] == 31) || (tx_cal_reg[0] == (-32))) &&
+ ((tx_cal_reg[3] == 31) || (tx_cal_reg[3] == (-32)))) {
PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n"));
PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION SATUATION !!\n"));
PHY_DEBUG(("[CAL] **************************************\n"));
@@ -1014,8 +918,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
PHY_DEBUG(("[CAL] apply tx_cal[2] = %d\n", tx_cal[2]));
PHY_DEBUG(("[CAL] apply tx_cal[3] = %d\n", tx_cal[3]));
- if (phw_data->revision == 0x2002) // 1st-cut
- {
+ if (phw_data->revision == 0x2002) { // 1st-cut
val &= 0x0000FFFF;
val |= ((_s32_to_s4(tx_cal[0]) << 28)|
(_s32_to_s4(tx_cal[1]) << 24)|
@@ -1024,9 +927,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
hw_set_dxx_reg(phw_data, 0x54, val);
PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val));
return 0;
- }
- else // 2nd-cut
- {
+ } else { // 2nd-cut
val &= 0x000003FF;
val |= ((_s32_to_s5(tx_cal[0]) << 27)|
(_s32_to_s6(tx_cal[1]) << 21)|
@@ -1078,7 +979,7 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data)
msleep(30); // 20060612.1.a 30ms delay. Add the follow 2 lines
//To adjust TXVGA to fit iq_mag_0 range from 1250 ~ 1750
- adjust_TXVGA_for_iq_mag( phw_data );
+ adjust_TXVGA_for_iq_mag(phw_data);
// a. Disable AGC
hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, ®_agc_ctrl3);
@@ -1092,16 +993,12 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data)
result = _tx_iq_calibration_loop_winbond(phw_data, 150, 100);
- if (result > 0)
- {
- if (phw_data->revision == 0x2002) // 1st-cut
- {
+ if (result > 0) {
+ if (phw_data->revision == 0x2002) { // 1st-cut
hw_get_dxx_reg(phw_data, 0x54, &val);
val &= 0x0000FFFF;
hw_set_dxx_reg(phw_data, 0x54, val);
- }
- else // 2nd-cut
- {
+ } else { // 2nd-cut
hw_get_dxx_reg(phw_data, 0x3C, &val);
val &= 0x000003FF;
hw_set_dxx_reg(phw_data, 0x3C, val);
@@ -1109,32 +1006,24 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data)
result = _tx_iq_calibration_loop_winbond(phw_data, 300, 200);
- if (result > 0)
- {
- if (phw_data->revision == 0x2002) // 1st-cut
- {
+ if (result > 0) {
+ if (phw_data->revision == 0x2002) { // 1st-cut
hw_get_dxx_reg(phw_data, 0x54, &val);
val &= 0x0000FFFF;
hw_set_dxx_reg(phw_data, 0x54, val);
- }
- else // 2nd-cut
- {
+ } else { // 2nd-cut
hw_get_dxx_reg(phw_data, 0x3C, &val);
val &= 0x000003FF;
hw_set_dxx_reg(phw_data, 0x3C, val);
}
result = _tx_iq_calibration_loop_winbond(phw_data, 500, 400);
- if (result > 0)
- {
- if (phw_data->revision == 0x2002) // 1st-cut
- {
+ if (result > 0) {
+ if (phw_data->revision == 0x2002) { // 1st-cut
hw_get_dxx_reg(phw_data, 0x54, &val);
val &= 0x0000FFFF;
hw_set_dxx_reg(phw_data, 0x54, val);
- }
- else // 2nd-cut
- {
+ } else { // 2nd-cut
hw_get_dxx_reg(phw_data, 0x3C, &val);
val &= 0x000003FF;
hw_set_dxx_reg(phw_data, 0x3C, val);
@@ -1143,20 +1032,16 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data)
result = _tx_iq_calibration_loop_winbond(phw_data, 700, 500);
- if (result > 0)
- {
+ if (result > 0) {
PHY_DEBUG(("[CAL] ** <_tx_iq_calibration> **************\n"));
PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION FAILURE !!\n"));
PHY_DEBUG(("[CAL] **************************************\n"));
- if (phw_data->revision == 0x2002) // 1st-cut
- {
+ if (phw_data->revision == 0x2002) { // 1st-cut
hw_get_dxx_reg(phw_data, 0x54, &val);
val &= 0x0000FFFF;
hw_set_dxx_reg(phw_data, 0x54, val);
- }
- else // 2nd-cut
- {
+ } else { // 2nd-cut
hw_get_dxx_reg(phw_data, 0x3C, &val);
val &= 0x000003FF;
hw_set_dxx_reg(phw_data, 0x3C, val);
@@ -1179,24 +1064,20 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data)
hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
#ifdef _DEBUG
- if (phw_data->revision == 0x2002) // 1st-cut
- {
+ if (phw_data->revision == 0x2002) { // 1st-cut
hw_get_dxx_reg(phw_data, 0x54, &val);
PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
tx_cal_reg[0] = _s4_to_s32((val & 0xF0000000) >> 28);
tx_cal_reg[1] = _s4_to_s32((val & 0x0F000000) >> 24);
tx_cal_reg[2] = _s4_to_s32((val & 0x00F00000) >> 20);
tx_cal_reg[3] = _s4_to_s32((val & 0x000F0000) >> 16);
- }
- else // 2nd-cut
- {
+ } else { // 2nd-cut
hw_get_dxx_reg(phw_data, 0x3C, &val);
PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val));
tx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
tx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21);
tx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15);
tx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10);
-
}
PHY_DEBUG(("[CAL] ** tx_cal_reg[0] = %d\n", tx_cal_reg[0]));
@@ -1236,8 +1117,8 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
u32 pwr_image;
u8 verify_count;
- s32 iqcal_tone_i_avg,iqcal_tone_q_avg;
- s32 iqcal_image_i_avg,iqcal_image_q_avg;
+ s32 iqcal_tone_i_avg, iqcal_tone_q_avg;
+ s32 iqcal_image_i_avg, iqcal_image_q_avg;
u16 capture_time;
PHY_DEBUG(("[CAL] -> [5]_rx_iq_calibration_loop()\n"));
@@ -1267,54 +1148,49 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
//for (loop = 0; loop < 1; loop++)
//for (loop = 0; loop < LOOP_TIMES; loop++)
loop = LOOP_TIMES;
- while (loop > 0)
- {
+ while (loop > 0) {
PHY_DEBUG(("[CAL] [%d.] <_rx_iq_calibration_loop>\n", (LOOP_TIMES-loop+1)));
- iqcal_tone_i_avg=0;
- iqcal_tone_q_avg=0;
- iqcal_image_i_avg=0;
- iqcal_image_q_avg=0;
- capture_time=0;
-
- for(capture_time=0; capture_time<10; capture_time++)
- {
- // i. Set "calib_start" to 0x0
- reg_mode_ctrl &= ~MASK_CALIB_START;
- if( !hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl) )//20060718.1 modify
- return 0;
- PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
-
- reg_mode_ctrl &= ~MASK_IQCAL_MODE;
- reg_mode_ctrl |= (MASK_CALIB_START|0x1);
- hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
- PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
-
- // c.
- hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
- PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
+ iqcal_tone_i_avg = 0;
+ iqcal_tone_q_avg = 0;
+ iqcal_image_i_avg = 0;
+ iqcal_image_q_avg = 0;
+ capture_time = 0;
+
+ for (capture_time = 0; capture_time < 10; capture_time++) {
+ // i. Set "calib_start" to 0x0
+ reg_mode_ctrl &= ~MASK_CALIB_START;
+ if (!hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl)) //20060718.1 modify
+ return 0;
+ PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
- iqcal_tone_i = _s13_to_s32(val & 0x00001FFF);
- iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13);
- PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n",
- iqcal_tone_i, iqcal_tone_q));
+ reg_mode_ctrl &= ~MASK_IQCAL_MODE;
+ reg_mode_ctrl |= (MASK_CALIB_START|0x1);
+ hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
+ PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
- hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
- PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
+ // c.
+ hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
+ PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
- iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
- iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
- PHY_DEBUG(("[CAL] ** iqcal_image_i = %d, iqcal_image_q = %d\n",
- iqcal_image_i, iqcal_image_q));
- if( capture_time == 0)
- {
+ iqcal_tone_i = _s13_to_s32(val & 0x00001FFF);
+ iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13);
+ PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n",
+ iqcal_tone_i, iqcal_tone_q));
+
+ hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
+ PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
+
+ iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
+ iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
+ PHY_DEBUG(("[CAL] ** iqcal_image_i = %d, iqcal_image_q = %d\n",
+ iqcal_image_i, iqcal_image_q));
+ if (capture_time == 0)
continue;
- }
- else
- {
- iqcal_image_i_avg=( iqcal_image_i_avg*(capture_time-1) +iqcal_image_i)/capture_time;
- iqcal_image_q_avg=( iqcal_image_q_avg*(capture_time-1) +iqcal_image_q)/capture_time;
- iqcal_tone_i_avg=( iqcal_tone_i_avg*(capture_time-1) +iqcal_tone_i)/capture_time;
- iqcal_tone_q_avg=( iqcal_tone_q_avg*(capture_time-1) +iqcal_tone_q)/capture_time;
+ else {
+ iqcal_image_i_avg = (iqcal_image_i_avg*(capture_time-1) + iqcal_image_i)/capture_time;
+ iqcal_image_q_avg = (iqcal_image_q_avg*(capture_time-1) + iqcal_image_q)/capture_time;
+ iqcal_tone_i_avg = (iqcal_tone_i_avg*(capture_time-1) + iqcal_tone_i)/capture_time;
+ iqcal_tone_q_avg = (iqcal_tone_q_avg*(capture_time-1) + iqcal_tone_q)/capture_time;
}
}
@@ -1340,8 +1216,7 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
PHY_DEBUG(("[CAL] ** rot_image_q_b = %d\n", rot_image_q_b));
// f.
- if (rot_tone_i_b == 0)
- {
+ if (rot_tone_i_b == 0) {
PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n"));
PHY_DEBUG(("[CAL] ** rot_tone_i_b=0 to calculate EPS and THETA !!\n"));
PHY_DEBUG(("[CAL] ******************************************\n"));
@@ -1363,8 +1238,7 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
PHY_DEBUG(("[CAL] ** sin(b/2)=%d, cos(b/2)=%d\n", sin_b, cos_b));
PHY_DEBUG(("[CAL] ** sin(b)=%d, cos(b)=%d\n", sin_2b, cos_2b));
- if (cos_2b == 0)
- {
+ if (cos_2b == 0) {
PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n"));
PHY_DEBUG(("[CAL] ** cos(b)=0 !!\n"));
PHY_DEBUG(("[CAL] ******************************************\n"));
@@ -1376,13 +1250,9 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
//temp2 = (41943040/cos_2b)*sin_b*(-1);
if (phw_data->revision == 0x2002) // 1st-cut
- {
temp2 = (41943040/cos_2b)*sin_b*(-1);
- }
else // 2nd-cut
- {
temp2 = (41943040*4/cos_2b)*sin_b*(-1);
- }
rx_cal_flt_b[0] = _floor(temp1/(32768+a_2));
rx_cal_flt_b[1] = _floor(temp2/(32768-a_2));
@@ -1410,16 +1280,14 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
PHY_DEBUG(("[CAL] ** pwr_tone = %d\n", pwr_tone));
PHY_DEBUG(("[CAL] ** pwr_image = %d\n", pwr_image));
- if (pwr_tone > pwr_image)
- {
+ if (pwr_tone > pwr_image) {
verify_count++;
PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *************\n"));
PHY_DEBUG(("[CAL] ** VERIFY OK # %d !!\n", verify_count));
PHY_DEBUG(("[CAL] ******************************************\n"));
- if (verify_count > 2)
- {
+ if (verify_count > 2) {
PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n"));
PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION OK !!\n"));
PHY_DEBUG(("[CAL] **************************************\n"));
@@ -1432,15 +1300,12 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
hw_get_dxx_reg(phw_data, 0x54, &val);
PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
- if (phw_data->revision == 0x2002) // 1st-cut
- {
+ if (phw_data->revision == 0x2002) { // 1st-cut
rx_cal_reg[0] = _s4_to_s32((val & 0x0000F000) >> 12);
rx_cal_reg[1] = _s4_to_s32((val & 0x00000F00) >> 8);
rx_cal_reg[2] = _s4_to_s32((val & 0x000000F0) >> 4);
rx_cal_reg[3] = _s4_to_s32((val & 0x0000000F));
- }
- else // 2nd-cut
- {
+ } else { // 2nd-cut
rx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
rx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21);
rx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15);
@@ -1452,22 +1317,17 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
PHY_DEBUG(("[CAL] rx_cal_reg[2] = %d\n", rx_cal_reg[2]));
PHY_DEBUG(("[CAL] rx_cal_reg[3] = %d\n", rx_cal_reg[3]));
- if (phw_data->revision == 0x2002) // 1st-cut
- {
- if (((rx_cal_reg[0]==7) || (rx_cal_reg[0]==(-8))) &&
- ((rx_cal_reg[3]==7) || (rx_cal_reg[3]==(-8))))
- {
+ if (phw_data->revision == 0x2002) { // 1st-cut
+ if (((rx_cal_reg[0] == 7) || (rx_cal_reg[0] == (-8))) &&
+ ((rx_cal_reg[3] == 7) || (rx_cal_reg[3] == (-8)))) {
PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n"));
PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION SATUATION !!\n"));
PHY_DEBUG(("[CAL] **************************************\n"));
break;
}
- }
- else // 2nd-cut
- {
- if (((rx_cal_reg[0]==31) || (rx_cal_reg[0]==(-32))) &&
- ((rx_cal_reg[3]==31) || (rx_cal_reg[3]==(-32))))
- {
+ } else { // 2nd-cut
+ if (((rx_cal_reg[0] == 31) || (rx_cal_reg[0] == (-32))) &&
+ ((rx_cal_reg[3] == 31) || (rx_cal_reg[3] == (-32)))) {
PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n"));
PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION SATUATION !!\n"));
PHY_DEBUG(("[CAL] **************************************\n"));
@@ -1485,17 +1345,14 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
PHY_DEBUG(("[CAL] apply rx_cal[3] = %d\n", rx_cal[3]));
hw_get_dxx_reg(phw_data, 0x54, &val);
- if (phw_data->revision == 0x2002) // 1st-cut
- {
+ if (phw_data->revision == 0x2002) { // 1st-cut
val &= 0x0000FFFF;
val |= ((_s32_to_s4(rx_cal[0]) << 12)|
(_s32_to_s4(rx_cal[1]) << 8)|
(_s32_to_s4(rx_cal[2]) << 4)|
(_s32_to_s4(rx_cal[3])));
hw_set_dxx_reg(phw_data, 0x54, val);
- }
- else // 2nd-cut
- {
+ } else { // 2nd-cut
val &= 0x000003FF;
val |= ((_s32_to_s5(rx_cal[0]) << 27)|
(_s32_to_s6(rx_cal[1]) << 21)|
@@ -1503,8 +1360,8 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
(_s32_to_s5(rx_cal[3]) << 10));
hw_set_dxx_reg(phw_data, 0x54, val);
- if( loop == 3 )
- return 0;
+ if (loop == 3)
+ return 0;
}
PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val));
@@ -1547,18 +1404,15 @@ void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency)
result = _rx_iq_calibration_loop_winbond(phw_data, 12589, frequency);
- if (result > 0)
- {
+ if (result > 0) {
_reset_rx_cal(phw_data);
result = _rx_iq_calibration_loop_winbond(phw_data, 7943, frequency);
- if (result > 0)
- {
+ if (result > 0) {
_reset_rx_cal(phw_data);
result = _rx_iq_calibration_loop_winbond(phw_data, 5011, frequency);
- if (result > 0)
- {
+ if (result > 0) {
PHY_DEBUG(("[CAL] ** <_rx_iq_calibration> **************\n"));
PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION FAILURE !!\n"));
PHY_DEBUG(("[CAL] **************************************\n"));
@@ -1571,15 +1425,12 @@ void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency)
hw_get_dxx_reg(phw_data, 0x54, &val);
PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
- if (phw_data->revision == 0x2002) // 1st-cut
- {
+ if (phw_data->revision == 0x2002) { // 1st-cut
rx_cal_reg[0] = _s4_to_s32((val & 0x0000F000) >> 12);
rx_cal_reg[1] = _s4_to_s32((val & 0x00000F00) >> 8);
rx_cal_reg[2] = _s4_to_s32((val & 0x000000F0) >> 4);
rx_cal_reg[3] = _s4_to_s32((val & 0x0000000F));
- }
- else // 2nd-cut
- {
+ } else { // 2nd-cut
rx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
rx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21);
rx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15);
@@ -1634,32 +1485,31 @@ void phy_calibration_winbond(struct hw_data *phw_data, u32 frequency)
}
//===========================
-void phy_set_rf_data( struct hw_data * pHwData, u32 index, u32 value )
+void phy_set_rf_data(struct hw_data * pHwData, u32 index, u32 value)
{
- u32 ltmp=0;
+ u32 ltmp = 0;
- switch( pHwData->phy_type )
- {
+ switch (pHwData->phy_type) {
case RF_MAXIM_2825:
case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331)
- ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 );
+ ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18);
break;
case RF_MAXIM_2827:
- ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 );
+ ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18);
break;
case RF_MAXIM_2828:
- ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 );
+ ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18);
break;
case RF_MAXIM_2829:
- ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 );
+ ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18);
break;
case RF_AIROHA_2230:
case RF_AIROHA_2230S: // 20060420 Add this
- ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( value, 20 );
+ ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(value, 20);
break;
case RF_AIROHA_7230:
@@ -1668,11 +1518,11 @@ void phy_set_rf_data( struct hw_data * pHwData, u32 index, u32 value )
case RF_WB_242:
case RF_WB_242_1: // 20060619.5 Add
- ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( value, 24 );
+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse(value, 24);
break;
}
- Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
+ Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
}
// 20060717 modify as Bruce's mail
@@ -1690,15 +1540,14 @@ unsigned char adjust_TXVGA_for_iq_mag(struct hw_data *phw_data)
reg_state = 0;
- for( init_txvga=0; init_txvga<10; init_txvga++)
- {
- current_txvga = ( 0x24C40A|(init_txvga<<6) );
- phy_set_rf_data(phw_data, 5, ((5<<24)|current_txvga) );
+ for (init_txvga = 0; init_txvga < 10; init_txvga++) {
+ current_txvga = (0x24C40A|(init_txvga<<6));
+ phy_set_rf_data(phw_data, 5, ((5<<24)|current_txvga));
phw_data->txvga_setting_for_cal = current_txvga;
msleep(30); // 20060612.1.a
- if( !hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl) ) // 20060718.1 modify
+ if (!hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl)) // 20060718.1 modify
return false;
PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
@@ -1731,19 +1580,17 @@ unsigned char adjust_TXVGA_for_iq_mag(struct hw_data *phw_data)
iq_mag_0_tx = (s32) _sqrt(sqsum);
PHY_DEBUG(("[CAL] ** auto_adjust_txvga_for_iq_mag_0_tx=%d\n", iq_mag_0_tx));
- if( iq_mag_0_tx>=700 && iq_mag_0_tx<=1750 )
+ if (iq_mag_0_tx >= 700 && iq_mag_0_tx <= 1750)
break;
- else if(iq_mag_0_tx > 1750)
- {
- init_txvga=-2;
+ else if (iq_mag_0_tx > 1750) {
+ init_txvga = -2;
continue;
- }
- else
+ } else
continue;
}
- if( iq_mag_0_tx>=700 && iq_mag_0_tx<=1750 )
+ if (iq_mag_0_tx >= 700 && iq_mag_0_tx <= 1750)
return true;
else
return false;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 06/15] Staging: winbond: Replace C99 comments with C88
2010-05-26 23:39 [PATCH 01/15] Staging: winbond: Fix spacing around brackets and colons Mike Sheldon
` (3 preceding siblings ...)
2010-05-26 23:39 ` [PATCH 05/15] Staging: winbond: Fix spacing around brackets, braces, etc Mike Sheldon
@ 2010-05-26 23:39 ` Mike Sheldon
2010-05-26 23:39 ` [PATCH 07/15] Staging: winbond: Replace printk usage with pr_err Mike Sheldon
` (9 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Mike Sheldon @ 2010-05-26 23:39 UTC (permalink / raw)
To: greg, pavel; +Cc: devel, linux-kernel, Mike Sheldon
This patches phy_calibration.c to replace all the C99 style comments (//) with C89 style (/* ... */), as reported by checkpatch.pl.
Signed-off-by: Mike Sheldon <mike@mikeasoft.com>
---
drivers/staging/winbond/phy_calibration.c | 387 ++++++++++++++---------------
1 files changed, 191 insertions(+), 196 deletions(-)
diff --git a/drivers/staging/winbond/phy_calibration.c b/drivers/staging/winbond/phy_calibration.c
index c007c06..e51b1e7 100644
--- a/drivers/staging/winbond/phy_calibration.c
+++ b/drivers/staging/winbond/phy_calibration.c
@@ -19,7 +19,7 @@
/****************** LOCAL CONSTANT AND MACRO SECTION ************************/
#define LOOP_TIMES 20
-#define US 1000//MICROSECOND
+#define US 1000 /*MICROSECOND*/
#define AG_CONST 0.6072529350
#define FIXED(X) ((s32)((X) * 32768.0))
@@ -33,8 +33,8 @@ static const s32 Angles[] = {
};
/****************** LOCAL FUNCTION DECLARATION SECTION **********************/
-//void _phy_rf_write_delay(struct hw_data *phw_data);
-//void phy_init_rf(struct hw_data *phw_data);
+/*void _phy_rf_write_delay(struct hw_data *phw_data); */
+/*void phy_init_rf(struct hw_data *phw_data); */
/****************** FUNCTION DEFINITION SECTION *****************************/
@@ -184,9 +184,9 @@ s32 _floor(s32 n)
}
/****************************************************************************/
-// The following code is sqare-root function.
-// sqsum is the input and the output is sq_rt;
-// The maximum of sqsum = 2^27 -1;
+/* The following code is sqare-root function.
+ * sqsum is the input and the output is sq_rt;
+ * The maximum of sqsum = 2^27 -1; */
u32 _sqrt(u32 sqsum)
{
u32 sq_rt;
@@ -260,8 +260,8 @@ void _sin_cos(s32 angle, s32 *sin, s32 *cos)
s32 X, Y, TargetAngle, CurrAngle;
unsigned Step;
- X = FIXED(AG_CONST); // AG_CONST * cos(0)
- Y = 0; // AG_CONST * sin(0)
+ X = FIXED(AG_CONST); /* AG_CONST * cos(0) */
+ Y = 0; /* AG_CONST * sin(0) */
TargetAngle = abs(angle);
CurrAngle = 0;
@@ -316,21 +316,21 @@ void _reset_rx_cal(struct hw_data *phw_data)
hw_get_dxx_reg(phw_data, 0x54, &val);
- if (phw_data->revision == 0x2002) // 1st-cut
+ if (phw_data->revision == 0x2002) /* 1st-cut */
val &= 0xFFFF0000;
- else // 2nd-cut
+ else /* 2nd-cut */
val &= 0x000003FF;
hw_set_dxx_reg(phw_data, 0x54, val);
}
-// ************for winbond calibration*********
-//
-
-//
-//
-// *********************************************
+/************for winbond calibration*********
+ *
+ *
+ *
+ *
+ *********************************************/
void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequency)
{
u32 reg_agc_ctrl3;
@@ -341,29 +341,29 @@ void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequen
PHY_DEBUG(("[CAL] -> [1]_rxadc_dc_offset_cancellation()\n"));
phy_init_rf(phw_data);
- // set calibration channel
+ /* set calibration channel */
if ((RF_WB_242 == phw_data->phy_type) ||
- (RF_WB_242_1 == phw_data->phy_type)) { // 20060619.5 Add
+ (RF_WB_242_1 == phw_data->phy_type)) { /* 20060619.5 Add */
if ((frequency >= 2412) && (frequency <= 2484)) {
- // w89rf242 change frequency to 2390Mhz
+ /* w89rf242 change frequency to 2390Mhz */
PHY_DEBUG(("[CAL] W89RF242/11G/Channel=2390Mhz\n"));
phy_set_rf_data(phw_data, 3, (3<<24)|0x025586);
}
}
- // reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel
+ /* reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel */
hw_get_dxx_reg(phw_data, 0x5C, &val);
val &= ~(0x03FF);
hw_set_dxx_reg(phw_data, 0x5C, val);
- // reset the TX and RX IQ calibration data
+ /* reset the TX and RX IQ calibration data */
hw_set_dxx_reg(phw_data, 0x3C, 0);
hw_set_dxx_reg(phw_data, 0x54, 0);
- hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed
+ hw_set_dxx_reg(phw_data, 0x58, 0x30303030); /* IQ_Alpha Changed */
- // a. Disable AGC
+ /* a. Disable AGC */
hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, ®_agc_ctrl3);
reg_agc_ctrl3 &= ~BIT(2);
reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
@@ -373,7 +373,7 @@ void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequen
val |= MASK_AGC_FIX_GAIN;
hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
- // b. Turn off BB RX
+ /* b. Turn off BB RX */
hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, ®_a_acq_ctrl);
reg_a_acq_ctrl |= MASK_AMER_OFF_REG;
hw_set_dxx_reg(phw_data, REG_A_ACQ_CTRL, reg_a_acq_ctrl);
@@ -382,9 +382,9 @@ void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequen
reg_b_acq_ctrl |= MASK_BMER_OFF_REG;
hw_set_dxx_reg(phw_data, REG_B_ACQ_CTRL, reg_b_acq_ctrl);
- // c. Make sure MAC is in receiving mode
- // d. Turn ON ADC calibration
- // - ADC calibrator is triggered by this signal rising from 0 to 1
+ /* c. Make sure MAC is in receiving mode */
+ /* d. Turn ON ADC calibration */
+ /* - ADC calibrator is triggered by this signal rising from 0 to 1 */
hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val);
val &= ~MASK_ADC_DC_CAL_STR;
hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val);
@@ -392,7 +392,7 @@ void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequen
val |= MASK_ADC_DC_CAL_STR;
hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val);
- // e. The result are shown in "adc_dc_cal_i[8:0] and adc_dc_cal_q[8:0]"
+ /* e. The result are shown in "adc_dc_cal_i[8:0] and adc_dc_cal_q[8:0]" */
#ifdef _DEBUG
hw_get_dxx_reg(phw_data, REG_OFFSET_READ, &val);
PHY_DEBUG(("[CAL] REG_OFFSET_READ = 0x%08X\n", val));
@@ -407,23 +407,22 @@ void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequen
val &= ~MASK_ADC_DC_CAL_STR;
hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val);
- // f. Turn on BB RX
- //hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, ®_a_acq_ctrl);
+ /* f. Turn on BB RX */
+ /* hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, ®_a_acq_ctrl); */
reg_a_acq_ctrl &= ~MASK_AMER_OFF_REG;
hw_set_dxx_reg(phw_data, REG_A_ACQ_CTRL, reg_a_acq_ctrl);
- //hw_get_dxx_reg(phw_data, REG_B_ACQ_CTRL, ®_b_acq_ctrl);
+ /* hw_get_dxx_reg(phw_data, REG_B_ACQ_CTRL, ®_b_acq_ctrl); */
reg_b_acq_ctrl &= ~MASK_BMER_OFF_REG;
hw_set_dxx_reg(phw_data, REG_B_ACQ_CTRL, reg_b_acq_ctrl);
- // g. Enable AGC
- //hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val);
+ /* g. Enable AGC */
+ /* hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val); */
reg_agc_ctrl3 |= BIT(2);
reg_agc_ctrl3 &= ~(MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
}
-
-////////////////////////////////////////////////////////
+/******************************************************/
void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data)
{
u32 reg_agc_ctrl3;
@@ -440,22 +439,22 @@ void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data)
PHY_DEBUG(("[CAL] -> [2]_txidac_dc_offset_cancellation()\n"));
- // a. Set to "TX calibration mode"
+ /* a. Set to "TX calibration mode" */
- //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits
+ /* 0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits */
phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2);
- //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit
+ /* 0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit */
phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6);
- //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized
+ /* 0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized */
phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A);
- //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized
+ /* 0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized */
phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C);
- //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode
+ /* 0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode */
phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
- hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed
+ hw_set_dxx_reg(phw_data, 0x58, 0x30303030); /* IQ_Alpha Changed */
- // a. Disable AGC
+ /* a. Disable AGC */
hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, ®_agc_ctrl3);
reg_agc_ctrl3 &= ~BIT(2);
reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
@@ -465,19 +464,19 @@ void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data)
val |= MASK_AGC_FIX_GAIN;
hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
- // b. set iqcal_mode[1:0] to 0x2 and set iqcal_tone[3:2] to 0
+ /* b. set iqcal_mode[1:0] to 0x2 and set iqcal_tone[3:2] to 0 */
hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl);
PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
- // mode=2, tone=0
- //reg_mode_ctrl |= (MASK_CALIB_START|2);
+ /* mode=2, tone=0 */
+ /* reg_mode_ctrl |= (MASK_CALIB_START|2); */
- // mode=2, tone=1
- //reg_mode_ctrl |= (MASK_CALIB_START|2|(1<<2));
+ /* mode=2, tone=1 */
+ /* reg_mode_ctrl |= (MASK_CALIB_START|2|(1<<2)); */
- // mode=2, tone=2
+ /* mode=2, tone=2 */
reg_mode_ctrl |= (MASK_CALIB_START|2|(2<<2));
hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
@@ -488,8 +487,8 @@ void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data)
for (loop = 0; loop < LOOP_TIMES; loop++) {
PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop));
- // c.
- // reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel
+ /* c. */
+ /* reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel */
reg_dc_cancel &= ~(0x03FF);
PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
@@ -504,7 +503,7 @@ void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data)
PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
mag_0, iqcal_image_i, iqcal_image_q));
- // d.
+ /* d. */
reg_dc_cancel |= (1 << CANCEL_DC_I_SHIFT);
PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
@@ -519,7 +518,7 @@ void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data)
PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
mag_1, iqcal_image_i, iqcal_image_q));
- // e. Calculate the correct DC offset cancellation value for I
+ /* e. Calculate the correct DC offset cancellation value for I */
if (mag_0 != mag_1)
fix_cancel_dc_i = (mag_0*10000) / (mag_0*10000 - mag_1*10000);
else {
@@ -544,13 +543,12 @@ void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data)
hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
- // g.
+ /* g. */
reg_mode_ctrl &= ~MASK_CALIB_START;
hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
}
-
-///////////////////////////////////////////////////////
+/*****************************************************/
void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data)
{
u32 reg_agc_ctrl3;
@@ -566,20 +564,20 @@ void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data)
int loop;
PHY_DEBUG(("[CAL] -> [3]_txqdac_dc_offset_cacellation()\n"));
- //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits
+ /* 0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits */
phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2);
- //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit
+ /* 0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit */
phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6);
- //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized
+ /* 0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized */
phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A);
- //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized
+ /* 0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized */
phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C);
- //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode
+ /* 0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode */
phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
- hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed
+ hw_set_dxx_reg(phw_data, 0x58, 0x30303030); /* IQ_Alpha Changed */
- // a. Disable AGC
+ /* a. Disable AGC */
hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, ®_agc_ctrl3);
reg_agc_ctrl3 &= ~BIT(2);
reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
@@ -589,11 +587,11 @@ void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data)
val |= MASK_AGC_FIX_GAIN;
hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
- // a. set iqcal_mode[1:0] to 0x3 and set iqcal_tone[3:2] to 0
+ /* a. set iqcal_mode[1:0] to 0x3 and set iqcal_tone[3:2] to 0 */
hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl);
PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
- //reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
+ /* reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); */
reg_mode_ctrl &= ~(MASK_IQCAL_MODE);
reg_mode_ctrl |= (MASK_CALIB_START|3);
hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
@@ -605,8 +603,8 @@ void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data)
for (loop = 0; loop < LOOP_TIMES; loop++) {
PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop));
- // b.
- // reset cancel_dc_q[4:0] in register DC_Cancel
+ /* b. */
+ /* reset cancel_dc_q[4:0] in register DC_Cancel */
reg_dc_cancel &= ~(0x001F);
PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
@@ -621,7 +619,7 @@ void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data)
PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
mag_0, iqcal_image_i, iqcal_image_q));
- // c.
+ /* c. */
reg_dc_cancel |= (1 << CANCEL_DC_Q_SHIFT);
PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
@@ -636,7 +634,7 @@ void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data)
PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
mag_1, iqcal_image_i, iqcal_image_q));
- // d. Calculate the correct DC offset cancellation value for I
+ /* d. Calculate the correct DC offset cancellation value for I */
if (mag_0 != mag_1) {
fix_cancel_dc_q = (mag_0*10000) / (mag_0*10000 - mag_1*10000);
} else {
@@ -662,13 +660,13 @@ void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data)
PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
- // f.
+ /* f. */
reg_mode_ctrl &= ~MASK_CALIB_START;
hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
}
-//20060612.1.a 20060718.1 Modify
+/* 20060612.1.a 20060718.1 Modify */
u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
s32 a_2_threshold,
s32 b_2_threshold)
@@ -712,11 +710,11 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
iqcal_tone_i_avg = 0;
iqcal_tone_q_avg = 0;
- if (!hw_set_dxx_reg(phw_data, 0x3C, 0x00)) // 20060718.1 modify
+ if (!hw_set_dxx_reg(phw_data, 0x3C, 0x00)) /* 20060718.1 modify */
return 0;
for (capture_time = 0; capture_time < 10; capture_time++) {
- // a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to
- // enable "IQ alibration Mode II"
+ /* a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to
+ enable "IQ alibration Mode II" */
reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
reg_mode_ctrl &= ~MASK_IQCAL_MODE;
reg_mode_ctrl |= (MASK_CALIB_START|0x02);
@@ -724,7 +722,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
- // b.
+ /* b. */
hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
@@ -738,21 +736,21 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
iq_mag_0_tx = (s32) _sqrt(sqsum);
PHY_DEBUG(("[CAL] ** iq_mag_0_tx=%d\n", iq_mag_0_tx));
- // c. Set "calib_start" to 0x0
+ /* c. Set "calib_start" to 0x0 */
reg_mode_ctrl &= ~MASK_CALIB_START;
hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
- // d. Set iqcal_mode[1:0] to 0x3 and set "calib_start" to 0x1 to
- // enable "IQ alibration Mode II"
- //hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val);
+ /* d. Set iqcal_mode[1:0] to 0x3 and set "calib_start" to 0x1 to
+ enable "IQ alibration Mode II" */
+ /* hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val); */
hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl);
reg_mode_ctrl &= ~MASK_IQCAL_MODE;
reg_mode_ctrl |= (MASK_CALIB_START|0x03);
hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
- // e.
+ /* e. */
hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
@@ -779,7 +777,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
PHY_DEBUG(("[CAL] ** rot_i_b = %d, rot_q_b = %d\n",
rot_i_b, rot_q_b));
- // f.
+ /* f. */
divisor = ((iq_mag_0_tx * iq_mag_0_tx * 2)/1024 - rot_i_b) * 2;
if (divisor == 0) {
@@ -797,8 +795,8 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
phw_data->iq_rsdl_gain_tx_d2 = a_2;
phw_data->iq_rsdl_phase_tx_d2 = b_2;
- //if ((abs(a_2) < 150) && (abs(b_2) < 100))
- //if ((abs(a_2) < 200) && (abs(b_2) < 200))
+ /* if ((abs(a_2) < 150) && (abs(b_2) < 100)) */
+ /* if ((abs(a_2) < 200) && (abs(b_2) < 200)) */
if ((abs(a_2) < a_2_threshold) && (abs(b_2) < b_2_threshold)) {
verify_count++;
@@ -830,13 +828,13 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
break;
}
- // 1280 * 32768 = 41943040
+ /* 1280 * 32768 = 41943040 */
temp1 = (41943040/cos_2b)*cos_b;
- //temp2 = (41943040/cos_2b)*sin_b*(-1);
- if (phw_data->revision == 0x2002) // 1st-cut
+ /* temp2 = (41943040/cos_2b)*sin_b*(-1); */
+ if (phw_data->revision == 0x2002) /* 1st-cut */
temp2 = (41943040/cos_2b)*sin_b*(-1);
- else // 2nd-cut
+ else /* 2nd-cut */
temp2 = (41943040*4/cos_2b)*sin_b*(-1);
tx_cal_flt_b[0] = _floor(temp1/(32768+a_2));
@@ -859,24 +857,24 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
PHY_DEBUG(("[CAL] tx_cal[2] = %d\n", tx_cal[2]));
PHY_DEBUG(("[CAL] tx_cal[3] = %d\n", tx_cal[3]));
- //if ((tx_cal[0] == 0) && (tx_cal[1] == 0) &&
- // (tx_cal[2] == 0) && (tx_cal[3] == 0))
- //{
- // PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n"));
- // PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION COMPLETE !!\n"));
- // PHY_DEBUG(("[CAL] ******************************************\n"));
- // return 0;
- //}
-
- // g.
- if (phw_data->revision == 0x2002) { // 1st-cut
+ /* if ((tx_cal[0] == 0) && (tx_cal[1] == 0) &&
+ (tx_cal[2] == 0) && (tx_cal[3] == 0))
+ {
+ PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n"));
+ PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION COMPLETE !!\n"));
+ PHY_DEBUG(("[CAL] ******************************************\n"));
+ return 0;
+ } */
+
+ /* g. */
+ if (phw_data->revision == 0x2002) { /* 1st-cut */
hw_get_dxx_reg(phw_data, 0x54, &val);
PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
tx_cal_reg[0] = _s4_to_s32((val & 0xF0000000) >> 28);
tx_cal_reg[1] = _s4_to_s32((val & 0x0F000000) >> 24);
tx_cal_reg[2] = _s4_to_s32((val & 0x00F00000) >> 20);
tx_cal_reg[3] = _s4_to_s32((val & 0x000F0000) >> 16);
- } else { // 2nd-cut
+ } else { /* 2nd-cut */
hw_get_dxx_reg(phw_data, 0x3C, &val);
PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val));
tx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
@@ -891,7 +889,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
PHY_DEBUG(("[CAL] tx_cal_reg[2] = %d\n", tx_cal_reg[2]));
PHY_DEBUG(("[CAL] tx_cal_reg[3] = %d\n", tx_cal_reg[3]));
- if (phw_data->revision == 0x2002) { // 1st-cut
+ if (phw_data->revision == 0x2002) { /* 1st-cut */
if (((tx_cal_reg[0] == 7) || (tx_cal_reg[0] == (-8))) &&
((tx_cal_reg[3] == 7) || (tx_cal_reg[3] == (-8)))) {
PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n"));
@@ -899,7 +897,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
PHY_DEBUG(("[CAL] **************************************\n"));
break;
}
- } else { // 2nd-cut
+ } else { /* 2nd-cut */
if (((tx_cal_reg[0] == 31) || (tx_cal_reg[0] == (-32))) &&
((tx_cal_reg[3] == 31) || (tx_cal_reg[3] == (-32)))) {
PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n"));
@@ -918,7 +916,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
PHY_DEBUG(("[CAL] apply tx_cal[2] = %d\n", tx_cal[2]));
PHY_DEBUG(("[CAL] apply tx_cal[3] = %d\n", tx_cal[3]));
- if (phw_data->revision == 0x2002) { // 1st-cut
+ if (phw_data->revision == 0x2002) { /* 1st-cut */
val &= 0x0000FFFF;
val |= ((_s32_to_s4(tx_cal[0]) << 28)|
(_s32_to_s4(tx_cal[1]) << 24)|
@@ -927,7 +925,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
hw_set_dxx_reg(phw_data, 0x54, val);
PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val));
return 0;
- } else { // 2nd-cut
+ } else { /* 2nd-cut */
val &= 0x000003FF;
val |= ((_s32_to_s5(tx_cal[0]) << 27)|
(_s32_to_s6(tx_cal[1]) << 21)|
@@ -938,7 +936,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
return 0;
}
- // i. Set "calib_start" to 0x0
+ /* i. Set "calib_start" to 0x0 */
reg_mode_ctrl &= ~MASK_CALIB_START;
hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
@@ -962,26 +960,26 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data)
PHY_DEBUG(("[CAL] -> [4]_tx_iq_calibration()\n"));
- //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits
+ /* 0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits */
phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2);
- //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit
- phy_set_rf_data(phw_data, 11, (11<<24)|0x19BDD6); // 20060612.1.a 0x1905D6);
- //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized
- phy_set_rf_data(phw_data, 5, (5<<24)|0x24C60A); //0x24C60A (high temperature)
- //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized
- phy_set_rf_data(phw_data, 6, (6<<24)|0x34880C); // 20060612.1.a 0x06890C);
- //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode
+ /* 0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit */
+ phy_set_rf_data(phw_data, 11, (11<<24)|0x19BDD6); /* 20060612.1.a 0x1905D6); */
+ /* 0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized */
+ phy_set_rf_data(phw_data, 5, (5<<24)|0x24C60A); /* 0x24C60A (high temperature) */
+ /* 0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized */
+ phy_set_rf_data(phw_data, 6, (6<<24)|0x34880C); /* 20060612.1.a 0x06890C); */
+ /* 0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode */
phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
- //; [BB-chip]: Calibration (6f).Send test pattern
- //; [BB-chip]: Calibration (6g). Search RXGCL optimal value
- //; [BB-chip]: Calibration (6h). Caculate TX-path IQ imbalance and setting TX path IQ compensation table
- //phy_set_rf_data(phw_data, 3, (3<<24)|0x025586);
+ /*; [BB-chip]: Calibration (6f).Send test pattern */
+ /*; [BB-chip]: Calibration (6g). Search RXGCL optimal value */
+ /*; [BB-chip]: Calibration (6h). Caculate TX-path IQ imbalance and setting TX path IQ compensation table */
+ /* phy_set_rf_data(phw_data, 3, (3<<24)|0x025586); */
- msleep(30); // 20060612.1.a 30ms delay. Add the follow 2 lines
- //To adjust TXVGA to fit iq_mag_0 range from 1250 ~ 1750
+ msleep(30); /* 20060612.1.a 30ms delay. Add the follow 2 lines */
+ /* To adjust TXVGA to fit iq_mag_0 range from 1250 ~ 1750 */
adjust_TXVGA_for_iq_mag(phw_data);
- // a. Disable AGC
+ /* a. Disable AGC */
hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, ®_agc_ctrl3);
reg_agc_ctrl3 &= ~BIT(2);
reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
@@ -994,11 +992,11 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data)
result = _tx_iq_calibration_loop_winbond(phw_data, 150, 100);
if (result > 0) {
- if (phw_data->revision == 0x2002) { // 1st-cut
+ if (phw_data->revision == 0x2002) { /* 1st-cut */
hw_get_dxx_reg(phw_data, 0x54, &val);
val &= 0x0000FFFF;
hw_set_dxx_reg(phw_data, 0x54, val);
- } else { // 2nd-cut
+ } else { /* 2nd-cut */
hw_get_dxx_reg(phw_data, 0x3C, &val);
val &= 0x000003FF;
hw_set_dxx_reg(phw_data, 0x3C, val);
@@ -1007,11 +1005,11 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data)
result = _tx_iq_calibration_loop_winbond(phw_data, 300, 200);
if (result > 0) {
- if (phw_data->revision == 0x2002) { // 1st-cut
+ if (phw_data->revision == 0x2002) { /* 1st-cut */
hw_get_dxx_reg(phw_data, 0x54, &val);
val &= 0x0000FFFF;
hw_set_dxx_reg(phw_data, 0x54, val);
- } else { // 2nd-cut
+ } else { /* 2nd-cut */
hw_get_dxx_reg(phw_data, 0x3C, &val);
val &= 0x000003FF;
hw_set_dxx_reg(phw_data, 0x3C, val);
@@ -1019,11 +1017,11 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data)
result = _tx_iq_calibration_loop_winbond(phw_data, 500, 400);
if (result > 0) {
- if (phw_data->revision == 0x2002) { // 1st-cut
+ if (phw_data->revision == 0x2002) { /* 1st-cut */
hw_get_dxx_reg(phw_data, 0x54, &val);
val &= 0x0000FFFF;
hw_set_dxx_reg(phw_data, 0x54, val);
- } else { // 2nd-cut
+ } else { /* 2nd-cut */
hw_get_dxx_reg(phw_data, 0x3C, &val);
val &= 0x000003FF;
hw_set_dxx_reg(phw_data, 0x3C, val);
@@ -1037,11 +1035,11 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data)
PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION FAILURE !!\n"));
PHY_DEBUG(("[CAL] **************************************\n"));
- if (phw_data->revision == 0x2002) { // 1st-cut
+ if (phw_data->revision == 0x2002) { /* 1st-cut */
hw_get_dxx_reg(phw_data, 0x54, &val);
val &= 0x0000FFFF;
hw_set_dxx_reg(phw_data, 0x54, val);
- } else { // 2nd-cut
+ } else { /* 2nd-cut */
hw_get_dxx_reg(phw_data, 0x3C, &val);
val &= 0x000003FF;
hw_set_dxx_reg(phw_data, 0x3C, val);
@@ -1051,27 +1049,27 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data)
}
}
- // i. Set "calib_start" to 0x0
+ /* i. Set "calib_start" to 0x0 */
hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl);
reg_mode_ctrl &= ~MASK_CALIB_START;
hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
- // g. Enable AGC
- //hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val);
+ /* g. Enable AGC */
+ /* hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val); */
reg_agc_ctrl3 |= BIT(2);
reg_agc_ctrl3 &= ~(MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
#ifdef _DEBUG
- if (phw_data->revision == 0x2002) { // 1st-cut
+ if (phw_data->revision == 0x2002) { /* 1st-cut */
hw_get_dxx_reg(phw_data, 0x54, &val);
PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
tx_cal_reg[0] = _s4_to_s32((val & 0xF0000000) >> 28);
tx_cal_reg[1] = _s4_to_s32((val & 0x0F000000) >> 24);
tx_cal_reg[2] = _s4_to_s32((val & 0x00F00000) >> 20);
tx_cal_reg[3] = _s4_to_s32((val & 0x000F0000) >> 16);
- } else { // 2nd-cut
+ } else { /* 2nd-cut */
hw_get_dxx_reg(phw_data, 0x3C, &val);
PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val));
tx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
@@ -1087,11 +1085,10 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data)
#endif
- // for test - BEN
- // RF Control Override
+ /* for test - BEN */
+ /* RF Control Override */
}
-
-/////////////////////////////////////////////////////////////////////////////////////////
+/***************************************************************************************/
u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 frequency)
{
u32 reg_mode_ctrl;
@@ -1125,28 +1122,28 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
PHY_DEBUG(("[CAL] ** factor = %d\n", factor));
-// RF Control Override
+/* RF Control Override */
hw_get_cxx_reg(phw_data, 0x80, &val);
val |= BIT(19);
hw_set_cxx_reg(phw_data, 0x80, val);
-// RF_Ctrl
+/* RF_Ctrl */
hw_get_cxx_reg(phw_data, 0xE4, &val);
val |= BIT(0);
hw_set_cxx_reg(phw_data, 0xE4, val);
PHY_DEBUG(("[CAL] ** RF_CTRL(0xE4) = 0x%08X", val));
- hw_set_dxx_reg(phw_data, 0x58, 0x44444444); // IQ_Alpha
+ hw_set_dxx_reg(phw_data, 0x58, 0x44444444); /* IQ_Alpha */
- // b.
+ /* b. */
hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl);
PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
verify_count = 0;
- //for (loop = 0; loop < 1; loop++)
- //for (loop = 0; loop < LOOP_TIMES; loop++)
+ /* for (loop = 0; loop < 1; loop++) */
+ /* for (loop = 0; loop < LOOP_TIMES; loop++) */
loop = LOOP_TIMES;
while (loop > 0) {
PHY_DEBUG(("[CAL] [%d.] <_rx_iq_calibration_loop>\n", (LOOP_TIMES-loop+1)));
@@ -1157,9 +1154,9 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
capture_time = 0;
for (capture_time = 0; capture_time < 10; capture_time++) {
- // i. Set "calib_start" to 0x0
+ /* i. Set "calib_start" to 0x0 */
reg_mode_ctrl &= ~MASK_CALIB_START;
- if (!hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl)) //20060718.1 modify
+ if (!hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl)) /* 20060718.1 modify */
return 0;
PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
@@ -1168,7 +1165,7 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
- // c.
+ /* c. */
hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
@@ -1200,7 +1197,7 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
iqcal_tone_i = iqcal_tone_i_avg;
iqcal_tone_q = iqcal_tone_q_avg;
- // d.
+ /* d. */
rot_tone_i_b = (iqcal_tone_i * iqcal_tone_i +
iqcal_tone_q * iqcal_tone_q) / 1024;
rot_tone_q_b = (iqcal_tone_i * iqcal_tone_q * (-1) +
@@ -1215,7 +1212,7 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
PHY_DEBUG(("[CAL] ** rot_image_i_b = %d\n", rot_image_i_b));
PHY_DEBUG(("[CAL] ** rot_image_q_b = %d\n", rot_image_q_b));
- // f.
+ /* f. */
if (rot_tone_i_b == 0) {
PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n"));
PHY_DEBUG(("[CAL] ** rot_tone_i_b=0 to calculate EPS and THETA !!\n"));
@@ -1245,13 +1242,13 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
break;
}
- // 1280 * 32768 = 41943040
+ /* 1280 * 32768 = 41943040 */
temp1 = (41943040/cos_2b)*cos_b;
- //temp2 = (41943040/cos_2b)*sin_b*(-1);
- if (phw_data->revision == 0x2002) // 1st-cut
+ /* temp2 = (41943040/cos_2b)*sin_b*(-1); */
+ if (phw_data->revision == 0x2002) /* 1st-cut */
temp2 = (41943040/cos_2b)*sin_b*(-1);
- else // 2nd-cut
+ else /* 2nd-cut */
temp2 = (41943040*4/cos_2b)*sin_b*(-1);
rx_cal_flt_b[0] = _floor(temp1/(32768+a_2));
@@ -1273,7 +1270,7 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
PHY_DEBUG(("[CAL] rx_cal[2] = %d\n", rx_cal[2]));
PHY_DEBUG(("[CAL] rx_cal[3] = %d\n", rx_cal[3]));
- // e.
+ /* e. */
pwr_tone = (iqcal_tone_i*iqcal_tone_i + iqcal_tone_q*iqcal_tone_q);
pwr_image = (iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q)*factor;
@@ -1296,16 +1293,16 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
continue;
}
- // g.
+ /* g. */
hw_get_dxx_reg(phw_data, 0x54, &val);
PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
- if (phw_data->revision == 0x2002) { // 1st-cut
+ if (phw_data->revision == 0x2002) { /* 1st-cut */
rx_cal_reg[0] = _s4_to_s32((val & 0x0000F000) >> 12);
rx_cal_reg[1] = _s4_to_s32((val & 0x00000F00) >> 8);
rx_cal_reg[2] = _s4_to_s32((val & 0x000000F0) >> 4);
rx_cal_reg[3] = _s4_to_s32((val & 0x0000000F));
- } else { // 2nd-cut
+ } else { /* 2nd-cut */
rx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
rx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21);
rx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15);
@@ -1317,7 +1314,7 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
PHY_DEBUG(("[CAL] rx_cal_reg[2] = %d\n", rx_cal_reg[2]));
PHY_DEBUG(("[CAL] rx_cal_reg[3] = %d\n", rx_cal_reg[3]));
- if (phw_data->revision == 0x2002) { // 1st-cut
+ if (phw_data->revision == 0x2002) { /* 1st-cut */
if (((rx_cal_reg[0] == 7) || (rx_cal_reg[0] == (-8))) &&
((rx_cal_reg[3] == 7) || (rx_cal_reg[3] == (-8)))) {
PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n"));
@@ -1325,7 +1322,7 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
PHY_DEBUG(("[CAL] **************************************\n"));
break;
}
- } else { // 2nd-cut
+ } else { /* 2nd-cut */
if (((rx_cal_reg[0] == 31) || (rx_cal_reg[0] == (-32))) &&
((rx_cal_reg[3] == 31) || (rx_cal_reg[3] == (-32)))) {
PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n"));
@@ -1345,14 +1342,14 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
PHY_DEBUG(("[CAL] apply rx_cal[3] = %d\n", rx_cal[3]));
hw_get_dxx_reg(phw_data, 0x54, &val);
- if (phw_data->revision == 0x2002) { // 1st-cut
+ if (phw_data->revision == 0x2002) { /* 1st-cut */
val &= 0x0000FFFF;
val |= ((_s32_to_s4(rx_cal[0]) << 12)|
(_s32_to_s4(rx_cal[1]) << 8)|
(_s32_to_s4(rx_cal[2]) << 4)|
(_s32_to_s4(rx_cal[3])));
hw_set_dxx_reg(phw_data, 0x54, val);
- } else { // 2nd-cut
+ } else { /* 2nd-cut */
val &= 0x000003FF;
val |= ((_s32_to_s5(rx_cal[0]) << 27)|
(_s32_to_s6(rx_cal[1]) << 21)|
@@ -1371,12 +1368,10 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
return 1;
}
-//////////////////////////////////////////////////////////
-
-//////////////////////////////////////////////////////////////////////////
+/*************************************************************************/
void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency)
{
-// figo 20050523 marked thsi flag for can't compile for relesase
+/* figo 20050523 marked thsi flag for can't compile for relesase */
#ifdef _DEBUG
s32 rx_cal_reg[4];
u32 val;
@@ -1385,22 +1380,22 @@ void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency)
u8 result;
PHY_DEBUG(("[CAL] -> [5]_rx_iq_calibration()\n"));
-// a. Set RFIC to "RX calibration mode"
- //; ----- Calibration (7). RX path IQ imbalance calibration loop
- // 0x01 0xFFBFC2 ; 3FEFF ; Calibration (7a). enable RX IQ calibration loop circuits
+ /* a. Set RFIC to "RX calibration mode" */
+ /*; ----- Calibration (7). RX path IQ imbalance calibration loop */
+ /* 0x01 0xFFBFC2 ; 3FEFF ; Calibration (7a). enable RX IQ calibration loop circuits */
phy_set_rf_data(phw_data, 1, (1<<24)|0xEFBFC2);
- // 0x0B 0x1A01D6 ; 06817 ; Calibration (7b). enable RX I/Q cal loop SW1 circuit
+ /* 0x0B 0x1A01D6 ; 06817 ; Calibration (7b). enable RX I/Q cal loop SW1 circuit */
phy_set_rf_data(phw_data, 11, (11<<24)|0x1A05D6);
- //0x05 0x24848A ; 09212 ; Calibration (7c). setting TX-VGA gain (TXGCH) to 2 --> to be optimized
+ /* 0x05 0x24848A ; 09212 ; Calibration (7c). setting TX-VGA gain (TXGCH) to 2 --> to be optimized */
phy_set_rf_data(phw_data, 5, (5<<24)| phw_data->txvga_setting_for_cal);
- //0x06 0x06840C ; 01A10 ; Calibration (7d). RXGCH=00; RXGCL=010 000 (RXVGA) --> to be optimized
+ /* 0x06 0x06840C ; 01A10 ; Calibration (7d). RXGCH=00; RXGCL=010 000 (RXVGA) --> to be optimized */
phy_set_rf_data(phw_data, 6, (6<<24)|0x06834C);
- //0x00 0xFFF1C0 ; 3F7C7 ; Calibration (7e). turn on IQ imbalance/Test mode
+ /* 0x00 0xFFF1C0 ; 3F7C7 ; Calibration (7e). turn on IQ imbalance/Test mode */
phy_set_rf_data(phw_data, 0, (0<<24)|0xFFF1C0);
- // ; [BB-chip]: Calibration (7f). Send test pattern
- // ; [BB-chip]: Calibration (7g). Search RXGCL optimal value
- // ; [BB-chip]: Calibration (7h). Caculate RX-path IQ imbalance and setting RX path IQ compensation table
+ /* ; [BB-chip]: Calibration (7f). Send test pattern */
+ /* ; [BB-chip]: Calibration (7g). Search RXGCL optimal value */
+ /* ; [BB-chip]: Calibration (7h). Caculate RX-path IQ imbalance and setting RX path IQ compensation table */
result = _rx_iq_calibration_loop_winbond(phw_data, 12589, frequency);
@@ -1425,12 +1420,12 @@ void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency)
hw_get_dxx_reg(phw_data, 0x54, &val);
PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
- if (phw_data->revision == 0x2002) { // 1st-cut
+ if (phw_data->revision == 0x2002) { /* 1st-cut */
rx_cal_reg[0] = _s4_to_s32((val & 0x0000F000) >> 12);
rx_cal_reg[1] = _s4_to_s32((val & 0x00000F00) >> 8);
rx_cal_reg[2] = _s4_to_s32((val & 0x000000F0) >> 4);
rx_cal_reg[3] = _s4_to_s32((val & 0x0000000F));
- } else { // 2nd-cut
+ } else { /* 2nd-cut */
rx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
rx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21);
rx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15);
@@ -1445,7 +1440,7 @@ void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency)
}
-////////////////////////////////////////////////////////////////////////
+/**********************************************************************/
void phy_calibration_winbond(struct hw_data *phw_data, u32 frequency)
{
u32 reg_mode_ctrl;
@@ -1453,7 +1448,7 @@ void phy_calibration_winbond(struct hw_data *phw_data, u32 frequency)
PHY_DEBUG(("[CAL] -> phy_calibration_winbond()\n"));
- // 20040701 1.1.25.1000 kevin
+ /* 20040701 1.1.25.1000 kevin */
hw_get_cxx_reg(phw_data, 0x80, &mac_ctrl);
hw_get_cxx_reg(phw_data, 0xE4, &rf_ctrl);
hw_get_dxx_reg(phw_data, 0x58, &iq_alpha);
@@ -1461,37 +1456,37 @@ void phy_calibration_winbond(struct hw_data *phw_data, u32 frequency)
_rxadc_dc_offset_cancellation_winbond(phw_data, frequency);
- //_txidac_dc_offset_cancellation_winbond(phw_data);
- //_txqdac_dc_offset_cacellation_winbond(phw_data);
+ /* _txidac_dc_offset_cancellation_winbond(phw_data); */
+ /* _txqdac_dc_offset_cacellation_winbond(phw_data); */
_tx_iq_calibration_winbond(phw_data);
_rx_iq_calibration_winbond(phw_data, frequency);
- //------------------------------------------------------------------------
+ /*------------------------------------------------------------------------*/
hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl);
- reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE|MASK_CALIB_START); // set when finish
+ reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE|MASK_CALIB_START); /* set when finish */
hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
- // i. Set RFIC to "Normal mode"
+ /* i. Set RFIC to "Normal mode" */
hw_set_cxx_reg(phw_data, 0x80, mac_ctrl);
hw_set_cxx_reg(phw_data, 0xE4, rf_ctrl);
hw_set_dxx_reg(phw_data, 0x58, iq_alpha);
- //------------------------------------------------------------------------
+ /*------------------------------------------------------------------------*/
phy_init_rf(phw_data);
}
-//===========================
+/*===========================*/
void phy_set_rf_data(struct hw_data * pHwData, u32 index, u32 value)
{
u32 ltmp = 0;
switch (pHwData->phy_type) {
case RF_MAXIM_2825:
- case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331)
+ case RF_MAXIM_V1: /* 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) */
ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18);
break;
@@ -1508,7 +1503,7 @@ void phy_set_rf_data(struct hw_data * pHwData, u32 index, u32 value)
break;
case RF_AIROHA_2230:
- case RF_AIROHA_2230S: // 20060420 Add this
+ case RF_AIROHA_2230S: /* 20060420 Add this */
ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(value, 20);
break;
@@ -1517,7 +1512,7 @@ void phy_set_rf_data(struct hw_data * pHwData, u32 index, u32 value)
break;
case RF_WB_242:
- case RF_WB_242_1: // 20060619.5 Add
+ case RF_WB_242_1: /* 20060619.5 Add */
ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse(value, 24);
break;
}
@@ -1525,7 +1520,7 @@ void phy_set_rf_data(struct hw_data * pHwData, u32 index, u32 value)
Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
}
-// 20060717 modify as Bruce's mail
+/* 20060717 modify as Bruce's mail */
unsigned char adjust_TXVGA_for_iq_mag(struct hw_data *phw_data)
{
int init_txvga = 0;
@@ -1545,15 +1540,15 @@ unsigned char adjust_TXVGA_for_iq_mag(struct hw_data *phw_data)
phy_set_rf_data(phw_data, 5, ((5<<24)|current_txvga));
phw_data->txvga_setting_for_cal = current_txvga;
- msleep(30); // 20060612.1.a
+ msleep(30); /* 20060612.1.a */
- if (!hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl)) // 20060718.1 modify
+ if (!hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl)) /* 20060718.1 modify */
return false;
PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
- // a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to
- // enable "IQ alibration Mode II"
+ /* a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to */
+ /* enable "IQ alibration Mode II" */
reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
reg_mode_ctrl &= ~MASK_IQCAL_MODE;
reg_mode_ctrl |= (MASK_CALIB_START|0x02);
@@ -1561,15 +1556,15 @@ unsigned char adjust_TXVGA_for_iq_mag(struct hw_data *phw_data)
hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
- udelay(1); // 20060612.1.a
+ udelay(1); /* 20060612.1.a */
- udelay(300); // 20060612.1.a
+ udelay(300); /* 20060612.1.a */
- // b.
+ /* b. */
hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
- udelay(300); // 20060612.1.a
+ udelay(300); /* 20060612.1.a */
iqcal_tone_i0 = _s13_to_s32(val & 0x00001FFF);
iqcal_tone_q0 = _s13_to_s32((val & 0x03FFE000) >> 13);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 07/15] Staging: winbond: Replace printk usage with pr_err
2010-05-26 23:39 [PATCH 01/15] Staging: winbond: Fix spacing around brackets and colons Mike Sheldon
` (4 preceding siblings ...)
2010-05-26 23:39 ` [PATCH 06/15] Staging: winbond: Replace C99 comments with C88 Mike Sheldon
@ 2010-05-26 23:39 ` Mike Sheldon
2010-05-26 23:39 ` [PATCH 08/15] Staging: winbond: Replace printk usage with pr_info/pr_err Mike Sheldon
` (8 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Mike Sheldon @ 2010-05-26 23:39 UTC (permalink / raw)
To: greg, pavel; +Cc: devel, linux-kernel, Mike Sheldon
Patches wb35reg.c to replace printk usage (missing KERN_ levels) with pr_err.
Signed-off-by: Mike Sheldon <mike@mikeasoft.com>
---
drivers/staging/winbond/wb35reg.c | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/staging/winbond/wb35reg.c b/drivers/staging/winbond/wb35reg.c
index 7707223..f245abe 100644
--- a/drivers/staging/winbond/wb35reg.c
+++ b/drivers/staging/winbond/wb35reg.c
@@ -151,7 +151,7 @@ unsigned char Wb35Reg_WriteSync(struct hw_data *pHwData, u16 RegisterNo, u32 Reg
if (ret < 0) {
#ifdef _PE_REG_DUMP_
- printk("EP0 Write register usb message sending error\n");
+ pr_err("EP0 Write register usb message sending error\n");
#endif
pHwData->SurpriseRemove = 1;
return false;
@@ -321,7 +321,7 @@ unsigned char Wb35Reg_ReadSync(struct hw_data *pHwData, u16 RegisterNo, u32 *pRe
if (ret < 0) {
#ifdef _PE_REG_DUMP_
- printk("EP0 Read register usb message sending error\n");
+ pr_err("EP0 Read register usb message sending error\n");
#endif
pHwData->SurpriseRemove = 1;
return false;
@@ -443,7 +443,7 @@ void Wb35Reg_EP0VM(struct hw_data *pHwData)
if (ret < 0) {
#ifdef _PE_REG_DUMP_
- printk("EP0 Irp sending error\n");
+ pr_err("EP0 Irp sending error\n");
#endif
goto cleanup;
}
@@ -480,7 +480,7 @@ void Wb35Reg_EP0VM_complete(struct urb *urb)
if (reg->EP0VM_status) {
#ifdef _PE_REG_DUMP_
- printk("EP0 IoCompleteRoutine return error\n");
+ pr_err("EP0 IoCompleteRoutine return error\n");
#endif
reg->EP0vm_state = VM_STOP;
pHwData->SurpriseRemove = 1;
@@ -527,7 +527,7 @@ void Wb35Reg_destroy(struct hw_data *pHwData)
kfree(reg_queue);
} else {
#ifdef _PE_REG_DUMP_
- printk("EP0 queue release error\n");
+ pr_err("EP0 queue release error\n");
#endif
}
spin_lock_irq(®->EP0VM_spin_lock);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 08/15] Staging: winbond: Replace printk usage with pr_info/pr_err
2010-05-26 23:39 [PATCH 01/15] Staging: winbond: Fix spacing around brackets and colons Mike Sheldon
` (5 preceding siblings ...)
2010-05-26 23:39 ` [PATCH 07/15] Staging: winbond: Replace printk usage with pr_err Mike Sheldon
@ 2010-05-26 23:39 ` Mike Sheldon
2010-05-26 23:39 ` [PATCH 09/15] Staging: winbond: Fix spacing around brackets and pointers Mike Sheldon
` (7 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Mike Sheldon @ 2010-05-26 23:39 UTC (permalink / raw)
To: greg, pavel; +Cc: devel, linux-kernel, Mike Sheldon
Patches wb35rx.c to replace printk usage (missing KERN_ levels) with appropriate pr_info and pr_err calls.
Signed-off-by: Mike Sheldon <mike@mikeasoft.com>
---
drivers/staging/winbond/wb35rx.c | 16 ++++++++--------
1 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/staging/winbond/wb35rx.c b/drivers/staging/winbond/wb35rx.c
index efe82b1..38ad5bd 100644
--- a/drivers/staging/winbond/wb35rx.c
+++ b/drivers/staging/winbond/wb35rx.c
@@ -28,7 +28,7 @@ static void packet_came(struct ieee80211_hw *hw, char *pRxBufferAddress, int Pac
skb = dev_alloc_skb(PacketSize);
if (!skb) {
- printk("Not enough memory for packet, FIXME\n");
+ pr_err("Not enough memory for packet, FIXME\n");
return;
}
@@ -110,7 +110,7 @@ static u16 Wb35Rx_indicate(struct ieee80211_hw *hw)
/* Basic check for Rx length. Is length valid? */
if (PacketSize > MAX_PACKET_SIZE) {
#ifdef _PE_RX_DUMP_
- printk("Serious ERROR : Rx data size too long, size =%d\n", PacketSize);
+ pr_err("Serious ERROR : Rx data size too long, size =%d\n", PacketSize);
#endif
pWb35Rx->EP3vm_state = VM_STOP;
@@ -187,7 +187,7 @@ static void Wb35Rx_Complete(struct urb *urb)
/* The URB is completed, check the result */
if (pWb35Rx->EP3VM_status != 0) {
#ifdef _PE_USB_STATE_DUMP_
- printk("EP3 IoCompleteRoutine return error\n");
+ pr_err("EP3 IoCompleteRoutine return error\n");
#endif
pWb35Rx->EP3vm_state = VM_STOP;
goto error;
@@ -250,7 +250,7 @@ static void Wb35Rx(struct ieee80211_hw *hw)
if (!pWb35Rx->RxOwner[RxBufferId]) {
/* It's impossible to run here. */
#ifdef _PE_RX_DUMP_
- printk("Rx driver fifo unavailable\n");
+ pr_err("Rx driver fifo unavailable\n");
#endif
goto error;
}
@@ -263,7 +263,7 @@ static void Wb35Rx(struct ieee80211_hw *hw)
pWb35Rx->pDRx = kzalloc(MAX_USB_RX_BUFFER, GFP_ATOMIC);
if (!pWb35Rx->pDRx) {
- printk("w35und: Rx memory alloc failed\n");
+ pr_err("w35und: Rx memory alloc failed\n");
goto error;
}
pRxBufferAddress = pWb35Rx->pDRx;
@@ -278,7 +278,7 @@ static void Wb35Rx(struct ieee80211_hw *hw)
retv = usb_submit_urb(urb, GFP_ATOMIC);
if (retv != 0) {
- printk("Rx URB sending error\n");
+ pr_err("Rx URB sending error\n");
goto error;
}
return;
@@ -338,7 +338,7 @@ void Wb35Rx_stop(struct hw_data *pHwData)
if (pWb35Rx->EP3vm_state == VM_RUNNING) {
usb_unlink_urb(pWb35Rx->RxUrb); /* Only use unlink, let Wb35Rx_destroy to free them */
#ifdef _PE_RX_DUMP_
- printk("EP3 Rx stop\n");
+ pr_info("EP3 Rx stop\n");
#endif
}
}
@@ -356,7 +356,7 @@ void Wb35Rx_destroy(struct hw_data *pHwData)
if (pWb35Rx->RxUrb)
usb_free_urb(pWb35Rx->RxUrb);
#ifdef _PE_RX_DUMP_
- printk("Wb35Rx_destroy OK\n");
+ pr_info("Wb35Rx_destroy OK\n");
#endif
}
--
1.7.0.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 09/15] Staging: winbond: Fix spacing around brackets and pointers.
2010-05-26 23:39 [PATCH 01/15] Staging: winbond: Fix spacing around brackets and colons Mike Sheldon
` (6 preceding siblings ...)
2010-05-26 23:39 ` [PATCH 08/15] Staging: winbond: Replace printk usage with pr_info/pr_err Mike Sheldon
@ 2010-05-26 23:39 ` Mike Sheldon
2010-05-26 23:39 ` [PATCH 10/15] Staging: winbond: Replace C99 comments with C88 Mike Sheldon
` (6 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Mike Sheldon @ 2010-05-26 23:39 UTC (permalink / raw)
To: greg, pavel; +Cc: devel, linux-kernel, Mike Sheldon
Patches wb35rx_f.h to correct the spacing around brackets and pointers as reported by checkpatch.pl
Signed-off-by: Mike Sheldon <mike@mikeasoft.com>
---
drivers/staging/winbond/wb35rx_f.h | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/winbond/wb35rx_f.h b/drivers/staging/winbond/wb35rx_f.h
index 98acce5..7885e51 100644
--- a/drivers/staging/winbond/wb35rx_f.h
+++ b/drivers/staging/winbond/wb35rx_f.h
@@ -7,9 +7,9 @@
//====================================
// Interface function declare
//====================================
-unsigned char Wb35Rx_initial( struct hw_data * pHwData );
-void Wb35Rx_destroy( struct hw_data * pHwData );
-void Wb35Rx_stop( struct hw_data * pHwData );
+unsigned char Wb35Rx_initial(struct hw_data *pHwData);
+void Wb35Rx_destroy(struct hw_data *pHwData);
+void Wb35Rx_stop(struct hw_data *pHwData);
void Wb35Rx_start(struct ieee80211_hw *hw);
#endif
--
1.7.0.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 10/15] Staging: winbond: Replace C99 comments with C88
2010-05-26 23:39 [PATCH 01/15] Staging: winbond: Fix spacing around brackets and colons Mike Sheldon
` (7 preceding siblings ...)
2010-05-26 23:39 ` [PATCH 09/15] Staging: winbond: Fix spacing around brackets and pointers Mike Sheldon
@ 2010-05-26 23:39 ` Mike Sheldon
2010-05-26 23:39 ` [PATCH 11/15] Staging: winbond: Fix spacing around brackets and pointers Mike Sheldon
` (5 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Mike Sheldon @ 2010-05-26 23:39 UTC (permalink / raw)
To: greg, pavel; +Cc: devel, linux-kernel, Mike Sheldon
This patches wb35rx_f.h to replace all the C99 style comments (//) with C89 style (/* ... */), as reported by checkpatch.pl.
Signed-off-by: Mike Sheldon <mike@mikeasoft.com>
---
drivers/staging/winbond/wb35rx_f.h | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/winbond/wb35rx_f.h b/drivers/staging/winbond/wb35rx_f.h
index 7885e51..706905a 100644
--- a/drivers/staging/winbond/wb35rx_f.h
+++ b/drivers/staging/winbond/wb35rx_f.h
@@ -4,9 +4,9 @@
#include <net/mac80211.h>
#include "wbhal_s.h"
-//====================================
-// Interface function declare
-//====================================
+/*************************************\
+ * Interface function declare *
+\*************************************/
unsigned char Wb35Rx_initial(struct hw_data *pHwData);
void Wb35Rx_destroy(struct hw_data *pHwData);
void Wb35Rx_stop(struct hw_data *pHwData);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 11/15] Staging: winbond: Fix spacing around brackets and pointers.
2010-05-26 23:39 [PATCH 01/15] Staging: winbond: Fix spacing around brackets and colons Mike Sheldon
` (8 preceding siblings ...)
2010-05-26 23:39 ` [PATCH 10/15] Staging: winbond: Replace C99 comments with C88 Mike Sheldon
@ 2010-05-26 23:39 ` Mike Sheldon
2010-05-26 23:39 ` [PATCH 12/15] Staging: winbond: Replace C99 comments with C88 Mike Sheldon
` (4 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Mike Sheldon @ 2010-05-26 23:39 UTC (permalink / raw)
To: greg, pavel; +Cc: devel, linux-kernel, Mike Sheldon
Patches wb35rx_s.h to correct the spacing around brackets and pointers as reported by checkpatch.pl
Signed-off-by: Mike Sheldon <mike@mikeasoft.com>
---
drivers/staging/winbond/wb35rx_s.h | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/staging/winbond/wb35rx_s.h b/drivers/staging/winbond/wb35rx_s.h
index 4b03274..7230a44 100644
--- a/drivers/staging/winbond/wb35rx_s.h
+++ b/drivers/staging/winbond/wb35rx_s.h
@@ -19,9 +19,9 @@ struct wb35_rx {
u32 ByteReceived;// For calculating throughput of BulkIn
atomic_t RxFireCounter;// Does Wb35Rx module fire?
- u8 RxBuffer[ MAX_USB_RX_BUFFER_NUMBER ][ ((MAX_USB_RX_BUFFER+3) & ~0x03 ) ];
- u16 RxBufferSize[ ((MAX_USB_RX_BUFFER_NUMBER+1) & ~0x01) ];
- u8 RxOwner[ ((MAX_USB_RX_BUFFER_NUMBER+3) & ~0x03 ) ];//Ownership of buffer 0: SW 1:HW
+ u8 RxBuffer[MAX_USB_RX_BUFFER_NUMBER][((MAX_USB_RX_BUFFER+3) & ~0x03)];
+ u16 RxBufferSize[((MAX_USB_RX_BUFFER_NUMBER+1) & ~0x01)];
+ u8 RxOwner[((MAX_USB_RX_BUFFER_NUMBER+3) & ~0x03)];//Ownership of buffer 0: SW 1:HW
u32 RxProcessIndex;//The next index to process
u32 RxBufferId;
@@ -36,9 +36,9 @@ struct wb35_rx {
u32 Rx3UrbCancel;
u32 LastR1; // For RSSI reporting
- struct urb * RxUrb;
+ struct urb *RxUrb;
u32 Ep3ErrorCount2; // 20060625.1 Usbd for Rx DMA error count
int EP3VM_status;
- u8 * pDRx;
+ u8 *pDRx;
};
--
1.7.0.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 12/15] Staging: winbond: Replace C99 comments with C88
2010-05-26 23:39 [PATCH 01/15] Staging: winbond: Fix spacing around brackets and colons Mike Sheldon
` (9 preceding siblings ...)
2010-05-26 23:39 ` [PATCH 11/15] Staging: winbond: Fix spacing around brackets and pointers Mike Sheldon
@ 2010-05-26 23:39 ` Mike Sheldon
2010-05-26 23:39 ` [PATCH 13/15] Staging: winbond: Replace printk usage with pr_info/pr_err Mike Sheldon
` (3 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Mike Sheldon @ 2010-05-26 23:39 UTC (permalink / raw)
To: greg, pavel; +Cc: devel, linux-kernel, Mike Sheldon
This patches wb35rx_s.h to replace all the C99 style comments (//) with C89 style (/* ... */), as reported by checkpatch.pl.
Signed-off-by: Mike Sheldon <mike@mikeasoft.com>
---
drivers/staging/winbond/wb35rx_s.h | 42 ++++++++++++++++++------------------
1 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/staging/winbond/wb35rx_s.h b/drivers/staging/winbond/wb35rx_s.h
index 7230a44..5cb48a0 100644
--- a/drivers/staging/winbond/wb35rx_s.h
+++ b/drivers/staging/winbond/wb35rx_s.h
@@ -1,43 +1,43 @@
-//============================================================================
-// wb35rx.h --
-//============================================================================
+/*============================================================================
+ * wb35rx.h --
+ *============================================================================*/
-// Definition for this module used
-#define MAX_USB_RX_BUFFER 4096 // This parameter must be 4096 931130.4.f
+/* Definition for this module used */
+#define MAX_USB_RX_BUFFER 4096 /* This parameter must be 4096 931130.4.f */
-#define MAX_USB_RX_BUFFER_NUMBER ETHERNET_RX_DESCRIPTORS // Maximum 254, 255 is RESERVED ID
-#define RX_INTERFACE 0 // Interface 1
-#define RX_PIPE 2 // Pipe 3
-#define MAX_PACKET_SIZE 1600 //1568 // 8 + 1532 + 4 + 24(IV EIV MIC ICV CRC) for check DMA data 931130.4.g
-#define RX_END_TAG 0x0badbeef
+#define MAX_USB_RX_BUFFER_NUMBER ETHERNET_RX_DESCRIPTORS /* Maximum 254, 255 is RESERVED ID */
+#define RX_INTERFACE 0 /* Interface 1 */
+#define RX_PIPE 2 /* Pipe 3 */
+#define MAX_PACKET_SIZE 1600 /* 1568 */ /* 8 + 1532 + 4 + 24(IV EIV MIC ICV CRC) for check DMA data 931130.4.g */
+#define RX_END_TAG 0x0badbeef
-//====================================
-// Internal variable for module
-//====================================
+/*====================================
+ * Internal variable for module
+ *====================================*/
struct wb35_rx {
- u32 ByteReceived;// For calculating throughput of BulkIn
- atomic_t RxFireCounter;// Does Wb35Rx module fire?
+ u32 ByteReceived; /* For calculating throughput of BulkIn */
+ atomic_t RxFireCounter; /* Does Wb35Rx module fire? */
u8 RxBuffer[MAX_USB_RX_BUFFER_NUMBER][((MAX_USB_RX_BUFFER+3) & ~0x03)];
u16 RxBufferSize[((MAX_USB_RX_BUFFER_NUMBER+1) & ~0x01)];
- u8 RxOwner[((MAX_USB_RX_BUFFER_NUMBER+3) & ~0x03)];//Ownership of buffer 0: SW 1:HW
+ u8 RxOwner[((MAX_USB_RX_BUFFER_NUMBER+3) & ~0x03)]; /* Ownership of buffer 0: SW 1:HW */
- u32 RxProcessIndex;//The next index to process
+ u32 RxProcessIndex; /* The next index to process */
u32 RxBufferId;
u32 EP3vm_state;
- u32 rx_halt; // For VM stopping
+ u32 rx_halt; /* For VM stopping */
u16 MoreDataSize;
u16 PacketSize;
- u32 CurrentRxBufferId; // For complete routine usage
+ u32 CurrentRxBufferId; /* For complete routine usage */
u32 Rx3UrbCancel;
- u32 LastR1; // For RSSI reporting
+ u32 LastR1; /* For RSSI reporting */
struct urb *RxUrb;
- u32 Ep3ErrorCount2; // 20060625.1 Usbd for Rx DMA error count
+ u32 Ep3ErrorCount2; /* 20060625.1 Usbd for Rx DMA error count */
int EP3VM_status;
u8 *pDRx;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 13/15] Staging: winbond: Replace printk usage with pr_info/pr_err
2010-05-26 23:39 [PATCH 01/15] Staging: winbond: Fix spacing around brackets and colons Mike Sheldon
` (10 preceding siblings ...)
2010-05-26 23:39 ` [PATCH 12/15] Staging: winbond: Replace C99 comments with C88 Mike Sheldon
@ 2010-05-26 23:39 ` Mike Sheldon
2010-05-26 23:39 ` [PATCH 14/15] Staging: winbond: Replace printk usage with pr_info Mike Sheldon
` (2 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Mike Sheldon @ 2010-05-26 23:39 UTC (permalink / raw)
To: greg, pavel; +Cc: devel, linux-kernel, Mike Sheldon
Patches wb35tx.c to replace printk usage (missing KERN_ levels) with appropriate pr_info and pr_err calls.
Signed-off-by: Mike Sheldon <mike@mikeasoft.com>
---
drivers/staging/winbond/wb35tx.c | 16 ++++++++--------
1 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/staging/winbond/wb35tx.c b/drivers/staging/winbond/wb35tx.c
index bda7a91..5ae792c 100644
--- a/drivers/staging/winbond/wb35tx.c
+++ b/drivers/staging/winbond/wb35tx.c
@@ -33,7 +33,7 @@ static void Wb35Tx_complete(struct urb * pUrb)
struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx;
struct wb35_mds *pMds = &adapter->Mds;
- printk("wb35: tx complete\n");
+ pr_info("wb35: tx complete\n");
// Variable setting
pWb35Tx->EP4vm_state = VM_COMPLETED;
pWb35Tx->EP4VM_status = pUrb->status; //Store the last result of Irp
@@ -49,7 +49,7 @@ static void Wb35Tx_complete(struct urb * pUrb)
// The URB is completed, check the result
if (pWb35Tx->EP4VM_status != 0) {
- printk("URB submission failed\n");
+ pr_err("URB submission failed\n");
pWb35Tx->EP4vm_state = VM_STOP;
goto error;
}
@@ -97,7 +97,7 @@ static void Wb35Tx(struct wbsoft_priv *adapter)
pWb35Tx->EP4vm_state = VM_RUNNING;
retv = usb_submit_urb(pUrb, GFP_ATOMIC);
if (retv<0) {
- printk("EP4 Tx Irp sending error\n");
+ pr_err("EP4 Tx Irp sending error\n");
goto cleanup;
}
@@ -154,14 +154,14 @@ void Wb35Tx_stop(struct hw_data * pHwData)
if (pWb35Tx->EP2vm_state == VM_RUNNING)
usb_unlink_urb( pWb35Tx->Tx2Urb ); // Only use unlink, let Wb35Tx_destrot to free them
#ifdef _PE_TX_DUMP_
- printk("EP2 Tx stop\n");
+ pr_info("EP2 Tx stop\n");
#endif
// Trying to canceling the Irp of EP4
if (pWb35Tx->EP4vm_state == VM_RUNNING)
usb_unlink_urb( pWb35Tx->Tx4Urb ); // Only use unlink, let Wb35Tx_destrot to free them
#ifdef _PE_TX_DUMP_
- printk("EP4 Tx stop\n");
+ pr_info("EP4 Tx stop\n");
#endif
}
@@ -183,7 +183,7 @@ void Wb35Tx_destroy(struct hw_data * pHwData)
usb_free_urb( pWb35Tx->Tx2Urb );
#ifdef _PE_TX_DUMP_
- printk("Wb35Tx_destroy OK\n");
+ pr_info("Wb35Tx_destroy OK\n");
#endif
}
@@ -230,7 +230,7 @@ static void Wb35Tx_EP2VM_complete(struct urb * pUrb)
//The Urb is completed, check the result
if (pWb35Tx->EP2VM_status != 0) {
- printk("EP2 IoCompleteRoutine return error\n");
+ pr_err("EP2 IoCompleteRoutine return error\n");
pWb35Tx->EP2vm_state= VM_STOP;
goto error;
}
@@ -280,7 +280,7 @@ static void Wb35Tx_EP2VM(struct wbsoft_priv *adapter)
if (retv < 0) {
#ifdef _PE_TX_DUMP_
- printk("EP2 Tx Irp sending error\n");
+ pr_err("EP2 Tx Irp sending error\n");
#endif
goto error;
}
--
1.7.0.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 14/15] Staging: winbond: Replace printk usage with pr_info
2010-05-26 23:39 [PATCH 01/15] Staging: winbond: Fix spacing around brackets and colons Mike Sheldon
` (11 preceding siblings ...)
2010-05-26 23:39 ` [PATCH 13/15] Staging: winbond: Replace printk usage with pr_info/pr_err Mike Sheldon
@ 2010-05-26 23:39 ` Mike Sheldon
2010-05-26 23:39 ` [PATCH 15/15] " Mike Sheldon
2010-06-18 17:03 ` [PATCH 01/15] Staging: winbond: Fix spacing around brackets and colons Greg KH
14 siblings, 0 replies; 16+ messages in thread
From: Mike Sheldon @ 2010-05-26 23:39 UTC (permalink / raw)
To: greg, pavel; +Cc: devel, linux-kernel, Mike Sheldon
Patches reg.c to replace printk usage (missing KERN_ levels) with pr_info.
Signed-off-by: Mike Sheldon <mike@mikeasoft.com>
---
drivers/staging/winbond/reg.c | 14 +++++++-------
1 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/staging/winbond/reg.c b/drivers/staging/winbond/reg.c
index d9a8128..ba2e705 100644
--- a/drivers/staging/winbond/reg.c
+++ b/drivers/staging/winbond/reg.c
@@ -1011,7 +1011,7 @@ void RFSynthesizer_initial(struct hw_data *pHwData)
/* Start to fill RF parameters, PLL_ON should be pulled low. */
Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000000);
#ifdef _PE_STATE_DUMP_
- printk("* PLL_ON low\n");
+ pr_info("* PLL_ON low\n");
#endif
number = sizeof(al7230_rf_data_24) / sizeof(al7230_rf_data_24[0]);
Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number);
@@ -1099,7 +1099,7 @@ void RFSynthesizer_initial(struct hw_data *pHwData)
/* RF parameters have filled completely, PLL_ON should be pulled high */
Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000080);
#ifdef _PE_STATE_DUMP_
- printk("* PLL_ON high\n");
+ pr_info("* PLL_ON high\n");
#endif
/* 2.4GHz */
@@ -1116,7 +1116,7 @@ void RFSynthesizer_initial(struct hw_data *pHwData)
/* 5GHz */
Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000000);
#ifdef _PE_STATE_DUMP_
- printk("* PLL_ON low\n");
+ pr_info("* PLL_ON low\n");
#endif
number = sizeof(al7230_rf_data_50) / sizeof(al7230_rf_data_50[0]);
@@ -1128,7 +1128,7 @@ void RFSynthesizer_initial(struct hw_data *pHwData)
Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000080);
#ifdef _PE_STATE_DUMP_
- printk("* PLL_ON high\n");
+ pr_info("* PLL_ON high\n");
#endif
ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F;
@@ -1796,7 +1796,7 @@ void RFSynthesizer_SwitchingChannel(struct hw_data *pHwData, struct chan_info C
/* Write to register. number must less and equal than 16 */
Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, number, NO_INCREMENT);
#ifdef _PE_STATE_DUMP_
- printk("Band changed\n");
+ pr_info("Band changed\n");
#endif
}
@@ -2338,9 +2338,9 @@ void EEPROMTxVgaAdjust(struct hw_data *pHwData)
}
#ifdef _PE_STATE_DUMP_
- printk(" TxVgaFor24 :\n");
+ pr_info(" TxVgaFor24 :\n");
DataDmp((u8 *)pHwData->TxVgaFor24, 14 , 0);
- printk(" TxVgaFor50 :\n");
+ pr_info(" TxVgaFor50 :\n");
DataDmp((u8 *)pHwData->TxVgaFor50, 70 , 0);
#endif
}
--
1.7.0.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 15/15] Staging: winbond: Replace printk usage with pr_info
2010-05-26 23:39 [PATCH 01/15] Staging: winbond: Fix spacing around brackets and colons Mike Sheldon
` (12 preceding siblings ...)
2010-05-26 23:39 ` [PATCH 14/15] Staging: winbond: Replace printk usage with pr_info Mike Sheldon
@ 2010-05-26 23:39 ` Mike Sheldon
2010-06-18 17:03 ` [PATCH 01/15] Staging: winbond: Fix spacing around brackets and colons Greg KH
14 siblings, 0 replies; 16+ messages in thread
From: Mike Sheldon @ 2010-05-26 23:39 UTC (permalink / raw)
To: greg, pavel; +Cc: devel, linux-kernel, Mike Sheldon
Patches wbusb.c to replace printk usage (missing KERN_ levels) with pr_info.
Signed-off-by: Mike Sheldon <mike@mikeasoft.com>
---
drivers/staging/winbond/wbusb.c | 20 ++++++++++----------
1 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/staging/winbond/wbusb.c b/drivers/staging/winbond/wbusb.c
index 681419d..1bad709 100644
--- a/drivers/staging/winbond/wbusb.c
+++ b/drivers/staging/winbond/wbusb.c
@@ -77,18 +77,18 @@ static int wbsoft_add_interface(struct ieee80211_hw *dev,
static void wbsoft_remove_interface(struct ieee80211_hw *dev,
struct ieee80211_vif *vif)
{
- printk("wbsoft_remove interface called\n");
+ pr_info("wbsoft_remove interface called\n");
}
static void wbsoft_stop(struct ieee80211_hw *hw)
{
- printk(KERN_INFO "%s called\n", __func__);
+ pr_info("%s called\n", __func__);
}
static int wbsoft_get_stats(struct ieee80211_hw *hw,
struct ieee80211_low_level_stats *stats)
{
- printk(KERN_INFO "%s called\n", __func__);
+ pr_info("%s called\n", __func__);
return 0;
}
@@ -159,13 +159,13 @@ static void hal_set_current_channel_ex(struct hw_data *pHwData, struct chan_info
if (pHwData->SurpriseRemove)
return;
- printk("Going to channel: %d/%d\n", channel.band, channel.ChanNo);
+ pr_info("Going to channel: %d/%d\n", channel.band, channel.ChanNo);
RFSynthesizer_SwitchingChannel(pHwData, channel); /* Switch channel */
pHwData->Channel = channel.ChanNo;
pHwData->band = channel.band;
#ifdef _PE_STATE_DUMP_
- printk("Set channel is %d, band =%d\n", pHwData->Channel,
+ pr_info("Set channel is %d, band =%d\n", pHwData->Channel,
pHwData->band);
#endif
reg->M28_MacControl &= ~0xff; /* Clean channel information field */
@@ -247,7 +247,7 @@ static int wbsoft_config(struct ieee80211_hw *dev, u32 changed)
struct wbsoft_priv *priv = dev->priv;
struct chan_info ch;
- printk("wbsoft_config called\n");
+ pr_info("wbsoft_config called\n");
/* Should use channel_num, or something, as that is already pre-translated */
ch.band = 1;
@@ -265,7 +265,7 @@ static int wbsoft_config(struct ieee80211_hw *dev, u32 changed)
static u64 wbsoft_get_tsf(struct ieee80211_hw *dev)
{
- printk("wbsoft_get_tsf called\n");
+ pr_info("wbsoft_get_tsf called\n");
return 0;
}
@@ -718,7 +718,7 @@ static int wb35_hw_init(struct ieee80211_hw *hw)
priv->sLocalPara.bAntennaNo = hal_get_antenna_number(pHwData);
#ifdef _PE_STATE_DUMP_
- printk("Driver init, antenna no = %d\n", psLOCAL->bAntennaNo);
+ pr_info("Driver init, antenna no = %d\n", psLOCAL->bAntennaNo);
#endif
hal_get_hw_radio_off(pHwData);
@@ -792,7 +792,7 @@ static int wb35_probe(struct usb_interface *intf,
endpoint = &interface->endpoint[0].desc;
if (endpoint[2].wMaxPacketSize == 512) {
- printk("[w35und] Working on USB 2.0\n");
+ pr_info("[w35und] Working on USB 2.0\n");
pWbUsb->IsUsb20 = 1;
}
@@ -850,7 +850,7 @@ static void wb35_hw_halt(struct wbsoft_priv *adapter)
/* Turn off Rx and Tx hardware ability */
hal_stop(&adapter->sHwData);
#ifdef _PE_USB_INI_DUMP_
- printk("[w35und] Hal_stop O.K.\n");
+ pr_info("[w35und] Hal_stop O.K.\n");
#endif
/* Waiting Irp completed */
msleep(100);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 01/15] Staging: winbond: Fix spacing around brackets and colons
2010-05-26 23:39 [PATCH 01/15] Staging: winbond: Fix spacing around brackets and colons Mike Sheldon
` (13 preceding siblings ...)
2010-05-26 23:39 ` [PATCH 15/15] " Mike Sheldon
@ 2010-06-18 17:03 ` Greg KH
14 siblings, 0 replies; 16+ messages in thread
From: Greg KH @ 2010-06-18 17:03 UTC (permalink / raw)
To: Mike Sheldon; +Cc: pavel, devel, linux-kernel
On Thu, May 27, 2010 at 12:39:38AM +0100, Mike Sheldon wrote:
> Patches mac_structures.h to correct the spacing around brackets and colons as reported by checkpatch.pl
This series doesn't apply at all, what tree did you make it against?
Can you redo it against the latest linux-next tree to make sure you got
all of the recent changes that happened in here for the 2.6.35-rc1
release and resend it?
thanks,
greg k-h
^ permalink raw reply [flat|nested] 16+ messages in thread