Re: [PATCH 2/2] KVM: SVM: Emulate next_rip svm feature

["Roedel, Joerg" <Joerg.Roedel@amd.com>]

On Tue, Jul 27, 2010 at 02:32:35PM -0400, Avi Kivity wrote:
>   On 07/27/2010 07:14 PM, Joerg Roedel wrote:
> > This patch implements the emulations of the svm next_rip
> > feature in the nested svm implementation in kvm.
> >
> > Signed-off-by: Joerg Roedel<joerg.roedel@amd.com>
> > ---
> >   arch/x86/kvm/svm.c |    8 +++++++-
> >   1 files changed, 7 insertions(+), 1 deletions(-)
> >
> > diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
> > index 7d10f2c..b44c9cc 100644
> > --- a/arch/x86/kvm/svm.c
> > +++ b/arch/x86/kvm/svm.c
> > @@ -1919,6 +1919,7 @@ static int nested_svm_vmexit(struct vcpu_svm *svm)
> >   	nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
> >   	nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
> >   	nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
> > +	nested_vmcb->control.next_rip          = vmcb->control.next_rip;
> >
> 
> Can it be really this simple?  Suppose we emulate a nested guest 
> instruction just before vmexit, doesn't that invalidate 
> vmcb->control.next_rip?  Can that happen?

Good point. I looked again into it. The documentation states:

	The next sequential instruction pointer (nRIP) is saved in
	the guest VMCB control area at location C8h on all #VMEXITs that
	are due to instruction intercepts, as defined in Section 15.8 on
	page 378, as well as MSR and IOIO intercepts and exceptions
	caused by the INT3, INTO, and BOUND instructions. For all other
	intercepts, nRIP is reset to zero.

There are a few intercepts that may need injection when running nested
immediatly after an instruction emulation on the host side:
	
	INTR, NMI
	#PF, #GP, ...

All these instructions do not provide a valid next_rip on #vmexit so we
should be save here. The other way around, copying back a next_rip
pointer when there should be none, should also not happen as far as I
see it. The next_rip is only set for instruction intercepts which are
either handled on the host side or reinjected directly into the L1
hypervisor.
When you don't see a failing case either, I think we are save with this
simple implementation.

	Joerg

-- 
Joerg Roedel - AMD Operating System Research Center

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