From: Andrew Morton <akpm@linux-foundation.org>
To: Shaohua Li <shaohua.li@intel.com>
Cc: lkml <linux-kernel@vger.kernel.org>, Ingo Molnar <mingo@elte.hu>,
Andi Kleen <andi@firstfloor.org>, "hpa@zytor.com" <hpa@zytor.com>
Subject: Re: [patch]x86: avoid unnecessary tlb flush
Date: Thu, 5 Aug 2010 22:19:13 -0700 [thread overview]
Message-ID: <20100805221913.4da0f8be.akpm@linux-foundation.org> (raw)
In-Reply-To: <1281065308.29094.5.camel@sli10-desk.sh.intel.com>
On Fri, 06 Aug 2010 11:28:28 +0800 Shaohua Li <shaohua.li@intel.com> wrote:
> In x86, access and dirty bits are set automatically by CPU when CPU accesses
> memory. When we go into the code path of below flush_tlb_nonprotect_page(),
> we already set dirty bit for pte and don't need flush tlb. This might mean
> tlb entry in some CPUs hasn't dirty bit set, but this doesn't matter. When
> the CPUs do page write, they will automatically check the bit and no software
> involved.
>
> On the other hand, flush tlb in below position is harmful. Test creates CPU
> number of threads, each thread writes to a same but random address in same vma
> range and we measure the total time. Under a 4 socket system, original time is
> 1.96s, while with the patch, the time is 0.8s. Under a 2 socket system, there is
> 20% time cut too. perf shows a lot of time are taking to send ipi/handle ipi for
> tlb flush.
>
> Signed-off-by: Shaohua Li <shaohua.li@intel.com>
>
> ---
> arch/x86/include/asm/pgtable.h | 3 +++
> include/asm-generic/pgtable.h | 4 ++++
> mm/memory.c | 2 +-
> 3 files changed, 8 insertions(+), 1 deletion(-)
>
> Index: linux/arch/x86/include/asm/pgtable.h
> ===================================================================
> --- linux.orig/arch/x86/include/asm/pgtable.h 2010-07-29 13:25:12.000000000 +0800
> +++ linux/arch/x86/include/asm/pgtable.h 2010-08-03 09:02:07.000000000 +0800
> @@ -603,6 +603,9 @@ static inline void ptep_set_wrprotect(st
> pte_update(mm, addr, ptep);
> }
>
> +#define __HAVE_ARCH_FLUSH_TLB_NONPROTECT_PAGE
> +#define flush_tlb_nonprotect_page(vma, address)
> +
> /*
> * clone_pgd_range(pgd_t *dst, pgd_t *src, int count);
> *
> Index: linux/include/asm-generic/pgtable.h
> ===================================================================
> --- linux.orig/include/asm-generic/pgtable.h 2010-07-29 13:25:12.000000000 +0800
> +++ linux/include/asm-generic/pgtable.h 2010-08-03 09:02:07.000000000 +0800
> @@ -129,6 +129,10 @@ static inline void ptep_set_wrprotect(st
> #define move_pte(pte, prot, old_addr, new_addr) (pte)
> #endif
>
> +#ifndef __HAVE_ARCH_FLUSH_TLB_NONPROTECT_PAGE
> +#define flush_tlb_nonprotect_page(vma, address) flush_tlb_page(vma, address)
> +#endif
The preferred technique here is
#ifndef flush_tlb_nonprotect_page
#define flush_tlb_nonprotect_page(vma, address) flush_tlb_page(vma, address)
#endif
so no need for __HAVE_ARCH_FLUSH_TLB_NONPROTECT_PAGE.
include/asm-generic/pgtable.h uses a mix of the two techniques.
next prev parent reply other threads:[~2010-08-06 5:19 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-08-06 3:28 [patch]x86: avoid unnecessary tlb flush Shaohua Li
2010-08-06 5:19 ` Andrew Morton [this message]
2010-08-13 0:47 ` Shaohua Li
2010-08-13 19:29 ` Hugh Dickins
2010-08-13 21:08 ` H. Peter Anvin
2010-08-13 23:00 ` Suresh Siddha
2010-08-16 1:16 ` Shaohua Li
2010-08-23 0:43 ` Shaohua Li
2010-08-23 17:57 ` [tip:x86/mm] x86, mm: Avoid unnecessary TLB flush tip-bot for Shaohua Li
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