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Date: Sun, 8 Aug 2010 01:48:03 +0400
From: Cyrill Gorcunov <gorcunov@gmail.com>
To: Ingo Molnar <mingo@elte.hu>
Cc: LKML <linux-kernel@vger.kernel.org>, Lin Ming <ming.m.lin@intel.com>,
        Stephane Eranian <eranian@google.com>,
        Peter Zijlstra <a.p.zijlstra@chello.nl>,
        Frederic Weisbecker <fweisbec@gmail.com>,
        "H. Peter Anvin" <hpa@zytor.com>
Subject: Re: [PATCH] perf,x86: P4 PMU -- update nmi irq statistics and
	unmask lvt entry properly
Message-ID: <20100807214803.GC10428@lenovo>
References: <20100805150917.GA6311@lenovo>
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On Thu, Aug 05, 2010 at 07:09:17PM +0400, Cyrill Gorcunov wrote:
> In case if last active performance counter is not overflowed at
> moment of NMI being triggered by another counter, the irq statistics
> may miss an update stage. As a more serious consequence -- apic quirk
> may not be triggered so apic lvt entry stay masked.
> 
> Tested-by: Lin Ming <ming.m.lin@intel.com>
> Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org>
> CC: Lin Ming <ming.m.lin@intel.com>
> CC: Stephane Eranian <eranian@google.com>
> CC: Peter Zijlstra <a.p.zijlstra@chello.nl>
> CC: Ingo Molnar <mingo@elte.hu>
> CC: Frederic Weisbecker <fweisbec@gmail.com>
> ---

Ping? Frederic, perhaps you'll pick it up?

	-- Cyrill