* [RFC -tip]
@ 2010-08-16 11:02 Cyrill Gorcunov
2010-08-17 9:14 ` Lin Ming
0 siblings, 1 reply; 3+ messages in thread
From: Cyrill Gorcunov @ 2010-08-16 11:02 UTC (permalink / raw)
To: Ingo Molnar, Stephane Eranian, Lin Ming
Cc: Frédéric Weisbecker, Arnaldo Carvalho de Melo, LKML,
Peter Zijlstra
Hi,
please review the approach, I can't test it due to lack
of hw (btw Ming, if you have some spare minutes -- mind to
pass some event as RAW and see how it goes?).
It just unifdef perf_event_p4.h and export it to user space.
Any complains are welcome. I've considered a separate header
file without #ifdef which would consists of definitions user
space may need but in result it become more messy then a few
#ifdefs in shared header.
-- Cyrill
---
perf, x86: Export RAW events specification to user space
P4 RAW events are tricky and need special bits passed from
userspace, we export RAW events specification so the user
space libraries may use it.
Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org>
CC: Lin Ming <ming.m.lin@intel.com>
CC: Stephane Eranian <eranian@google.com>
CC: Ingo Molnar <mingo@elte.hu>
CC: Frédéric Weisbecker <fweisbec@gmail.com>
CC: Arnaldo Carvalho de Melo <acme@redhat.com>
CC: Peter Zijlstra <peterz@infradead.org>
---
arch/x86/include/asm/Kbuild | 1 +
arch/x86/include/asm/perf_event_p4.h | 35 +++++++++++++++++++++++++++++++----
2 files changed, 32 insertions(+), 4 deletions(-)
Index: linux-2.6.git/arch/x86/include/asm/Kbuild
=====================================================================
--- linux-2.6.git.orig/arch/x86/include/asm/Kbuild
+++ linux-2.6.git/arch/x86/include/asm/Kbuild
@@ -24,3 +24,4 @@ unifdef-y += unistd_32.h
unifdef-y += unistd_64.h
unifdef-y += vm86.h
unifdef-y += vsyscall.h
+unifdef-y += perf_event_p4.h
Index: linux-2.6.git/arch/x86/include/asm/perf_event_p4.h
=====================================================================
--- linux-2.6.git.orig/arch/x86/include/asm/perf_event_p4.h
+++ linux-2.6.git/arch/x86/include/asm/perf_event_p4.h
@@ -5,6 +5,8 @@
#ifndef PERF_EVENT_P4_H
#define PERF_EVENT_P4_H
+#ifdef __KERNEL__
+
#include <linux/cpu.h>
#include <linux/bitops.h>
@@ -92,10 +94,16 @@
#define P4_ESCR_EMASK_BIT(class, name) class##__##name
/*
- * config field is 64bit width and consists of
- * HT << 63 | ESCR << 32 | CCCR
- * where HT is HyperThreading bit (since ESCR
- * has it reserved we may use it for own purpose)
+ * the config field is 64 bit width and has the following format
+ *
+ * Bits Meaning
+ * ----- -------
+ * 0-6 Metric value from enum P4_PEBS_METRIC (optional)
+ * 7-11 Reserved
+ * 12-31 Bits 12-31 of CCCR register (Intel SDM Vol 3)
+ * 32-56 Bits 0-24 of ESCR register (Intel SDM Vol 3)
+ * 57-62 Event key from enum P4_EVENTS
+ * 63 We use it to track event migration between HT threads
*
* note that this is NOT the addresses of respective
* ESCR and CCCR but rather an only packed value should
@@ -206,6 +214,21 @@ static inline u32 p4_default_escr_conf(i
return escr;
}
+#endif /* __KERNEL__ */
+
+/*
+ * RAW events specification
+ *
+ * Bits Meaning
+ * ----- -------
+ * 0-6 Metric value from enum P4_PEBS_METRIC (if needed)
+ * 7-11 Reserved, set to 0
+ * 12-31 Bits 12-31 of CCCR register (Intel SDM Vol 3)
+ * 32-56 Bits 0-24 of ESCR register (Intel SDM Vol 3)
+ * 57-62 Event key from enum P4_EVENTS
+ * 63 Reserved, set to 0
+ */
+
/*
* This are the events which should be used in "Event Select"
* field of ESCR register, they are like unique keys which allow
@@ -261,6 +284,8 @@ enum P4_EVENTS {
P4_EVENT_INSTR_COMPLETED,
};
+#ifdef __KERNEL__
+
#define P4_OPCODE(event) event##_OPCODE
#define P4_OPCODE_ESEL(opcode) ((opcode & 0x00ff) >> 0)
#define P4_OPCODE_EVNT(opcode) ((opcode & 0xff00) >> 8)
@@ -780,6 +805,8 @@ enum P4_ESCR_EMASKS {
#define p4_config_pebs_has(v, mask) (p4_config_unpack_pebs(v) & (mask))
+#endif /* __KERNEL__ */
+
enum P4_PEBS_METRIC {
P4_PEBS_METRIC__none,
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [RFC -tip]
2010-08-16 11:02 [RFC -tip] Cyrill Gorcunov
@ 2010-08-17 9:14 ` Lin Ming
2010-08-17 14:10 ` Cyrill Gorcunov
0 siblings, 1 reply; 3+ messages in thread
From: Lin Ming @ 2010-08-17 9:14 UTC (permalink / raw)
To: Cyrill Gorcunov
Cc: Ingo Molnar, Stephane Eranian, Frédéric Weisbecker,
Arnaldo Carvalho de Melo, LKML, Peter Zijlstra
On Mon, 2010-08-16 at 19:02 +0800, Cyrill Gorcunov wrote:
> Hi,
>
> please review the approach, I can't test it due to lack
> of hw (btw Ming, if you have some spare minutes -- mind to
> pass some event as RAW and see how it goes?).
#raw event for cpu cycles
perf top -e r3000020c0403c000
#raw event for cache-misses
perf top -e r120e00030803e000
I tried some raw events and it works.
>
> It just unifdef perf_event_p4.h and export it to user space.
>
> Any complains are welcome. I've considered a separate header
> file without #ifdef which would consists of definitions user
> space may need but in result it become more messy then a few
> #ifdefs in shared header.
>
> -- Cyrill
> ---
> perf, x86: Export RAW events specification to user space
>
> P4 RAW events are tricky and need special bits passed from
> userspace, we export RAW events specification so the user
> space libraries may use it.
>
> Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org>
> CC: Lin Ming <ming.m.lin@intel.com>
> CC: Stephane Eranian <eranian@google.com>
> CC: Ingo Molnar <mingo@elte.hu>
> CC: Frédéric Weisbecker <fweisbec@gmail.com>
> CC: Arnaldo Carvalho de Melo <acme@redhat.com>
> CC: Peter Zijlstra <peterz@infradead.org>
> ---
> arch/x86/include/asm/Kbuild | 1 +
> arch/x86/include/asm/perf_event_p4.h | 35 +++++++++++++++++++++++++++++++----
> 2 files changed, 32 insertions(+), 4 deletions(-)
>
> Index: linux-2.6.git/arch/x86/include/asm/Kbuild
> =====================================================================
> --- linux-2.6.git.orig/arch/x86/include/asm/Kbuild
> +++ linux-2.6.git/arch/x86/include/asm/Kbuild
> @@ -24,3 +24,4 @@ unifdef-y += unistd_32.h
> unifdef-y += unistd_64.h
> unifdef-y += vm86.h
> unifdef-y += vsyscall.h
> +unifdef-y += perf_event_p4.h
+header-y += perf_event_p4.h
Need to update this to header-y.
Thanks,
Lin Ming
> Index: linux-2.6.git/arch/x86/include/asm/perf_event_p4.h
> =====================================================================
> --- linux-2.6.git.orig/arch/x86/include/asm/perf_event_p4.h
> +++ linux-2.6.git/arch/x86/include/asm/perf_event_p4.h
> @@ -5,6 +5,8 @@
> #ifndef PERF_EVENT_P4_H
> #define PERF_EVENT_P4_H
>
> +#ifdef __KERNEL__
> +
> #include <linux/cpu.h>
> #include <linux/bitops.h>
>
> @@ -92,10 +94,16 @@
> #define P4_ESCR_EMASK_BIT(class, name) class##__##name
>
> /*
> - * config field is 64bit width and consists of
> - * HT << 63 | ESCR << 32 | CCCR
> - * where HT is HyperThreading bit (since ESCR
> - * has it reserved we may use it for own purpose)
> + * the config field is 64 bit width and has the following format
> + *
> + * Bits Meaning
> + * ----- -------
> + * 0-6 Metric value from enum P4_PEBS_METRIC (optional)
> + * 7-11 Reserved
> + * 12-31 Bits 12-31 of CCCR register (Intel SDM Vol 3)
> + * 32-56 Bits 0-24 of ESCR register (Intel SDM Vol 3)
> + * 57-62 Event key from enum P4_EVENTS
> + * 63 We use it to track event migration between HT threads
> *
> * note that this is NOT the addresses of respective
> * ESCR and CCCR but rather an only packed value should
> @@ -206,6 +214,21 @@ static inline u32 p4_default_escr_conf(i
> return escr;
> }
>
> +#endif /* __KERNEL__ */
> +
> +/*
> + * RAW events specification
> + *
> + * Bits Meaning
> + * ----- -------
> + * 0-6 Metric value from enum P4_PEBS_METRIC (if needed)
> + * 7-11 Reserved, set to 0
> + * 12-31 Bits 12-31 of CCCR register (Intel SDM Vol 3)
> + * 32-56 Bits 0-24 of ESCR register (Intel SDM Vol 3)
> + * 57-62 Event key from enum P4_EVENTS
> + * 63 Reserved, set to 0
> + */
> +
> /*
> * This are the events which should be used in "Event Select"
> * field of ESCR register, they are like unique keys which allow
> @@ -261,6 +284,8 @@ enum P4_EVENTS {
> P4_EVENT_INSTR_COMPLETED,
> };
>
> +#ifdef __KERNEL__
> +
> #define P4_OPCODE(event) event##_OPCODE
> #define P4_OPCODE_ESEL(opcode) ((opcode & 0x00ff) >> 0)
> #define P4_OPCODE_EVNT(opcode) ((opcode & 0xff00) >> 8)
> @@ -780,6 +805,8 @@ enum P4_ESCR_EMASKS {
>
> #define p4_config_pebs_has(v, mask) (p4_config_unpack_pebs(v) & (mask))
>
> +#endif /* __KERNEL__ */
> +
> enum P4_PEBS_METRIC {
> P4_PEBS_METRIC__none,
>
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [RFC -tip]
2010-08-17 9:14 ` Lin Ming
@ 2010-08-17 14:10 ` Cyrill Gorcunov
0 siblings, 0 replies; 3+ messages in thread
From: Cyrill Gorcunov @ 2010-08-17 14:10 UTC (permalink / raw)
To: Lin Ming
Cc: Ingo Molnar, Stephane Eranian, Frédéric Weisbecker,
Arnaldo Carvalho de Melo, LKML, Peter Zijlstra
On Tue, Aug 17, 2010 at 05:14:01PM +0800, Lin Ming wrote:
> On Mon, 2010-08-16 at 19:02 +0800, Cyrill Gorcunov wrote:
> > Hi,
> >
> > please review the approach, I can't test it due to lack
> > of hw (btw Ming, if you have some spare minutes -- mind to
> > pass some event as RAW and see how it goes?).
>
> #raw event for cpu cycles
> perf top -e r3000020c0403c000
>
> #raw event for cache-misses
> perf top -e r120e00030803e000
>
Ming, I had something different in mind, I'll prepare the case
to be tested. Will notify you. Thanks!
> I tried some raw events and it works.
>
> > Index: linux-2.6.git/arch/x86/include/asm/Kbuild
> > =====================================================================
> > --- linux-2.6.git.orig/arch/x86/include/asm/Kbuild
> > +++ linux-2.6.git/arch/x86/include/asm/Kbuild
> > @@ -24,3 +24,4 @@ unifdef-y += unistd_32.h
> > unifdef-y += unistd_64.h
> > unifdef-y += vm86.h
> > unifdef-y += vsyscall.h
> > +unifdef-y += perf_event_p4.h
>
> +header-y += perf_event_p4.h
>
> Need to update this to header-y.
Yeah, thanks for catching this!
>
> Thanks,
> Lin Ming
>
...
-- Cyrill
^ permalink raw reply [flat|nested] 3+ messages in thread
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2010-08-17 9:14 ` Lin Ming
2010-08-17 14:10 ` Cyrill Gorcunov
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