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From: Zhenyu Wang <zhenyuw@linux.intel.com>
To: Takashi Iwai <tiwai@suse.de>
Cc: Eric Anholt <eric@anholt.net>, David Airlie <airlied@linux.ie>,
	dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] agp/intel: Fix dma mask for Sandybridge
Date: Mon, 23 Aug 2010 14:19:22 +0800	[thread overview]
Message-ID: <20100823061922.GD29442@zhen-devel.sh.intel.com> (raw)
In-Reply-To: <s5hzkwddfy5.wl%tiwai@suse.de>

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On 2010.08.23 08:02:42 +0200, Takashi Iwai wrote:
> 
> Also, I don't understand the logic of 40bit addr calculation:
> 
> > static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge,
> >                                             dma_addr_t addr, int type)
> > {
> >         /* Shift high bits down */
> >        addr |= (addr >> 28) & 0xff;
> 
> Isn't it 0xff0?
> 

No. This depends on hw 32bit PTE format for sandybridge.

bit 31			 bit 11			 bit 4			bit 0
   |<-physical addr 31:12->|<-physical addr 39:32->|<-cache ctl 3:1->|valid|

-- 
Open Source Technology Center, Intel ltd.

$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827

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  parent reply	other threads:[~2010-08-23  6:19 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-08-20 15:36 [PATCH] agp/intel: Fix dma mask for Sandybridge Takashi Iwai
2010-08-23  1:35 ` Zhenyu Wang
2010-08-23  5:29   ` Takashi Iwai
2010-08-23  5:43     ` Zhenyu Wang
2010-08-23  6:02       ` Takashi Iwai
2010-08-23  6:13         ` Takashi Iwai
2010-08-23  6:19         ` Zhenyu Wang [this message]
2010-08-23  6:31           ` Takashi Iwai
2010-08-23  6:48             ` Zhenyu Wang
2010-08-23 14:02               ` Eric Anholt

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