Re: [PATCH -v3] perf, x86: try to handle unknown nmis with running perfctrs

Peter Zijlstra
2010-08-19T10:46:12Z

On Tue, 2010-08-17 at 17:22 +0200, Robert Richter wrote:
> + this_nmi = percpu_read(irq_stat.__nmi_count);
> + if (handled > 1)
> + goto mark_nmi;
> + if ((__get_cpu_var(nmi).marked == this_nmi)
> + && (__get_cpu_var(nmi).handled > 1))
> + /*
> + * We could have two subsequent back-to-back nmis: The
> + * first handles more than one counter, the 2nd
> + * handles only one counter and the 3rd handles no
> + * counter.
> + *
> + * This is the 2nd nmi because the previous was
> + * handling more than one counter. We will mark the
> + * next (3rd) and then drop it if unhandled.
> + */
> + goto mark_nmi;
> +
> + /* this may not trigger back-to-back nmis */
> + return NOTIFY_STOP;
> +
> + mark_nmi:
> + /* the next nmi could be a back-to-back nmi */
> + __get_cpu_var(nmi).marked = this_nmi + 1;
> + __get_cpu_var(nmi).handled = handled;
>
> return NOTIFY_STOP;
> }

I queued it with that part changed to:

+ this_nmi = percpu_read(irq_stat.__nmi_count);
+ if ((handled > 1) ||
+ /* the next nmi could be a back-to-back nmi */
+ ((__get_cpu_var(nmi).marked == this_nmi) &&
+ (__get_cpu_var(nmi).handled > 1))) {
+ /*
+ * We could have two subsequent back-to-back nmis: The
+ * first handles more than one counter, the 2nd
+ * handles only one counter and the 3rd handles no
+ * counter.
+ *
+ * This is the 2nd nmi because the previous was
+ * handling more than one counter. We will mark the
+ * next (3rd) and then drop it if unhandled.
+ */
+ __get_cpu_var(nmi).marked = this_nmi + 1;
+ __get_cpu_var(nmi).handled = handled;
+ }

return NOTIFY_STOP;
}