Re: [PATCH 4/4] [x86] perf: fix accidentally ack'ing a second event on intel perf counter

Robert Richter
2010-09-01T17:59:38Z

On 01.09.10 09:04:45, Stephane Eranian wrote:
> Don,
>
> Found your patch on LKML (I am not on it).
>
> In your changelog you said:
>
> > During testing of a patch to stop having the perf subsytem swallow nmis,
> > it was uncovered that Nehalem boxes were randomly getting unknown nmis
> > when using the perf tool.
> >
> > Moving the ack'ing of the PMI closer to when we get the status allows
> > the hardware to properly re-set the PMU bit signaling another PMI was
> > triggered during the processing of the first PMI. This allows the new
> > logic for dealing with the shortcomings of multiple PMIs to handle the
> > extra NMI by 'eat'ing it later.
>
> > Now one can wonder why are we getting a second PMI when we disable all
> > the PMUs in the beginning of the NMI handler to prevent such a case, for
> > that I do not know. But I know the fix below helps deal with this quirk.
> >
>
> I am assuming you're talking about back-to-back NMIs here, not nested NMIs.
> I don't quite understand the scenario here. Is it the case that you handled 1
> overflow, and then right as you return from the interrupt, you get a second
> PMI with a ovfl_status=0 ?
>
> What events did you measure? Which counters did you use?
> Did you have HT turned on?

It is related to this thread:

http://lkml.org/lkml/2010/8/25/124

Not acking the status immediately triggered an nmi, but the status was
0. Acking after reading and before processing the counters results in
a non-zero status and thus, no empty nmi.

-Robert

>
> > Tested on multiple Nehalems where the problem was occuring. With the
> > patch, the code now loops a second time to handle the second PMI (whereas
> > before it was not).
>

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Advanced Micro Devices, Inc.
Operating System Research Center