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Date: Wed, 29 Sep 2010 17:01:40 +0200
From: Robert Richter <robert.richter@amd.com>
To: Stephane Eranian <eranian@google.com>
CC: "mingo@redhat.com" <mingo@redhat.com>, "hpa@zytor.com" <hpa@zytor.com>,
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Subject: Re: [tip:perf/urgent] perf, x86: Catch spurious interrupts after
 disabling counters
Message-ID: <20100929150140.GK13563@erda.amd.com>
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On 29.09.10 09:28:56, Stephane Eranian wrote:
> On Wed, Sep 29, 2010 at 3:13 PM, Stephane Eranian <eranian@google.com> wrote:
> > On Wed, Sep 29, 2010 at 2:54 PM, Robert Richter <robert.richter@amd.com> wrote:
> >> On 29.09.10 14:53:01, Robert Richter wrote:
> >>> Stephane,
> >>>
> >>> On 29.09.10 08:26:41, Stephane Eranian wrote:
> >>> > You've applied the fix only to the generic X86 interrupt handler
> >>> > which is currently used by AMD64 processors.
> >>>
> >>> (... and P4).
> >>>

> Well, in tip-x86, I don't see your fix in p4_pmu_handle_irq(). Is
> that pending?

Right, I wasn't remembering correctly, it was P6 and core. And yes, P4
requires the fix. Will send a patch for this.

-Robert

-- 
Advanced Micro Devices, Inc.
Operating System Research Center