[PATCH] AMD, MCE thresholding: Fix the MCi_MISCj iteration order

[PATCH] AMD, MCE thresholding: Fix the MCi_MISCj iteration order

[Borislav Petkov]

The current code contains a subtle problem of checking only the Valid
bit of MSR0000_0413 (which is MC4_MISC0) in its first iteration and
breaking out if the bit is cleared.

However, MC4_MISC0[BlkPtr] is not predicated on MCi_STATUS[MiscV] or
MC4_MISC0[Valid] and should be checked prior to iterating over the
MCI_MISCj thresholding group only.

Fix this by decoupling the Valid bit check, which is part of the DRAM
thresholding group on F10h in the first iteration of the loop, from the
BlkPtr check.

Cc: <stable@kernel.org>
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
---
 arch/x86/kernel/cpu/mcheck/mce_amd.c |    9 +++------
 1 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 5e97529..39aaee5 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -141,6 +141,7 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
 				address = (low & MASK_BLKPTR_LO) >> 21;
 				if (!address)
 					break;
+
 				address += MCG_XBLK_ADDR;
 			} else
 				++address;
@@ -148,12 +149,8 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
 			if (rdmsr_safe(address, &low, &high))
 				break;
 
-			if (!(high & MASK_VALID_HI)) {
-				if (block)
-					continue;
-				else
-					break;
-			}
+			if (!(high & MASK_VALID_HI))
+				continue;
 
 			if (!(high & MASK_CNTP_HI)  ||
 			     (high & MASK_LOCKED_HI))
-- 
1.7.3.1.50.g1e633


-- 
Regards/Gruss,
Boris.

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