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Date: Tue, 26 Oct 2010 18:41:34 +0200
From: Borislav Petkov <bp@amd64.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Peter Zijlstra <peterz@infradead.org>,
        Markus Trippelsdorf <markus@trippelsdorf.de>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
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        Ingo Molnar <mingo@elte.hu>,
        Andreas Herrmann <andreas.herrmann3@amd.com>
Subject: Re: Clocksource tsc unstable (delta = -8589361717 ns) in current
 git
Message-ID: <20101026164134.GA2449@kryptos.osrc.amd.com>
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From: Thomas Gleixner <tglx@linutronix.de>
Date: Tue, Oct 26, 2010 at 05:46:00PM +0200

> On Tue, 26 Oct 2010, Peter Zijlstra wrote:
> 
> > On Tue, 2010-10-26 at 15:58 +0200, Markus Trippelsdorf wrote:
> > > > 
> > > > This is strange, tsc is actually stable on your F10h revC.
> > > 
> > > Yes. constant_tsc is among the CPU flags. 
> >  
> > constant_tsc only means the TSC is not affected by cpu freq changes.
> > 
> > It has zero relevance to cross-cpu sync of the TSC. The clocksource
> > stuff requires your TSC to be synchronous over all your CPUs.
> 
> That and not affected by C-States either.

Well, F10h TSC is P- and C-state invariant - I've never seen any systems
not passing the TSC sync check at boot so far. And if there are still
systems where this is not the case or you see the TSC not behaving, make
sure to tell me about it.

Besides, the TSC calibration with PIT seems to function ok, and the
"Detected " line shows reasonable core frequency. FWIW, I have a similar
configuration here and will run latest -git on it too to check.

-- 
Regards/Gruss,
Boris.

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