Re: [rfc 1/3] perf, x86: P4 PMU - describe config format

Cyrill Gorcunov
2010-11-26T13:07:33Z

On 11/26/10, Peter Zijlstra <peterz@infradead.org> wrote:
> On Fri, 2010-11-26 at 13:48 +0100, Stephane Eranian wrote:
>> Reviewed-by: Stephane Eranian <eranian@google.com>
>
> The new one, right? The one that reads:
>

yes, it's updated

> + * Low 32 bits
> + * -----------
> + * 0-6: P4_PEBS_METRIC enum
> + * 7-11: reserved
> + * 12: reserved (Enable)
> + * 13-15: reserved (ESCR select)
> + * 16-17: Active Thread
> + * 18: Compare
> + * 19: Complement
> + * 20-23: Threshold
> + * 24: Edge
> + * 25: reserved (FORCE_OVF)
> + * 26: reserved (OVF_PMI_T0)
> + * 27: reserved (OVF_PMI_T1)
> + * 28-29: reserved
> + * 30: reserved (Cascade)
> + * 31: reserved (OVF)
> + *
> + * High 32 bits
> + * ------------
> + * 0: reserved (T1_USR)
> + * 1: reserved (T1_OS)
> + * 2: reserved (T0_USR)
> + * 3: reserved (T0_OS)
> + * 4: Tag Enable
> + * 5-8: Tag Value
> + * 9-24: Event Mask (may use P4_ESCR_EMASK_BIT helper)
> + * 25-30: enum P4_EVENTS
> + * 31: reserved (HT thread)
>
>