Re: [rfc 1/3] perf, x86: P4 PMU - describe config format

Stephane Eranian
2010-11-26T13:07:24Z

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On Fri, Nov 26, 2010 at 1:59 PM, Peter Zijlstra <peterz@infradead.org> wrote:
> On Fri, 2010-11-26 at 13:48 +0100, Stephane Eranian wrote:
>> Reviewed-by: Stephane Eranian <eranian@google.com>
>
> The new one, right? The one that reads:
>
Yes. Sorry about that.

> + * Â  Â Low 32 bits
> + * Â  Â -----------
> + * Â  Â  Â 0-6: P4_PEBS_METRIC enum
> + * Â  Â  7-11: Â  Â  Â  Â  Â  Â  Â  Â  Â  Â reserved
> + * Â  Â  Â  12: Â  Â  Â  Â  Â  Â  Â  Â  Â  Â reserved (Enable)
> + * Â  Â 13-15: Â  Â  Â  Â  Â  Â  Â  Â  Â  Â reserved (ESCR select)
> + * Â  Â 16-17: Active Thread
> + * Â  Â  Â  18: Compare
> + * Â  Â  Â  19: Complement
> + * Â  Â 20-23: Threshold
> + * Â  Â  Â  24: Edge
> + * Â  Â  Â  25: Â  Â  Â  Â  Â  Â  Â  Â  Â  Â reserved (FORCE_OVF)
> + * Â  Â  Â  26: Â  Â  Â  Â  Â  Â  Â  Â  Â  Â reserved (OVF_PMI_T0)
> + * Â  Â  Â  27: Â  Â  Â  Â  Â  Â  Â  Â  Â  Â reserved (OVF_PMI_T1)
> + * Â  Â 28-29: Â  Â  Â  Â  Â  Â  Â  Â  Â  Â reserved
> + * Â  Â  Â  30: Â  Â  Â  Â  Â  Â  Â  Â  Â  Â reserved (Cascade)
> + * Â  Â  Â  31: Â  Â  Â  Â  Â  Â  Â  Â  Â  Â reserved (OVF)
> + *
> + * Â  Â High 32 bits
> + * Â  Â ------------
> + * Â  Â  Â  Â 0: Â  Â  Â  Â  Â  Â  Â  Â  Â  Â reserved (T1_USR)
> + * Â  Â  Â  Â 1: Â  Â  Â  Â  Â  Â  Â  Â  Â  Â reserved (T1_OS)
> + * Â  Â  Â  Â 2: Â  Â  Â  Â  Â  Â  Â  Â  Â  Â reserved (T0_USR)
> + * Â  Â  Â  Â 3: Â  Â  Â  Â  Â  Â  Â  Â  Â  Â reserved (T0_OS)
> + * Â  Â  Â  Â 4: Tag Enable
> + * Â  Â  Â 5-8: Tag Value
> + * Â  Â  9-24: Event Mask (may use P4_ESCR_EMASK_BIT helper)
> + * Â  Â 25-30: enum P4_EVENTS
> + * Â  Â  Â  31: Â  Â  Â  Â  Â  Â  Â  Â  Â  Â reserved (HT thread)
>
>
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