[PATCH] adding gpmc configuration functions, west bridge related

[PATCH] adding gpmc configuration functions, west bridge related

[Sutharsan]

This patch adds and exports gpmc configuration functions. 
'gpmc' configuration functions will be used by westbridge device controller driver.

Thanks,
Sutharsan

Signed-off-by: Sutharsan Ramamoorthy <srmt@cypress.com>
---

diff -uprN -X linux-2.6.37_vanilla/Documentation/dontdiff linux-2.6.37_vanilla/arch/arm/mach-omap2/Makefile linux-2.6.37-cywb/arch/arm/mach-omap2/Makefile
--- linux-2.6.37_vanilla/arch/arm/mach-omap2/Makefile	2010-11-29 20:42:04.000000000 -0800
+++ linux-2.6.37-cywb/arch/arm/mach-omap2/Makefile	2010-12-13 16:04:08.378446603 -0800
@@ -182,6 +182,7 @@ obj-y					+= $(usbfs-m) $(usbfs-y)
 obj-y					+= usb-musb.o
 obj-$(CONFIG_MACH_OMAP2_TUSB6010)	+= usb-tusb6010.o
 obj-y					+= usb-ehci.o
+obj-$(CONFIG_WESTBRIDGE_ASTORIA)        += usb-cywb-pnand.o
 
 onenand-$(CONFIG_MTD_ONENAND_OMAP2)	:= gpmc-onenand.o
 obj-y					+= $(onenand-m) $(onenand-y)
diff -uprN -X linux-2.6.37_vanilla/Documentation/dontdiff linux-2.6.37_vanilla/arch/arm/mach-omap2/usb-cywb-pnand.c linux-2.6.37-cywb/arch/arm/mach-omap2/usb-cywb-pnand.c
--- linux-2.6.37_vanilla/arch/arm/mach-omap2/usb-cywb-pnand.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-2.6.37-cywb/arch/arm/mach-omap2/usb-cywb-pnand.c	2010-12-14 15:51:13.710787480 -0800
@@ -0,0 +1,182 @@
+/*
+ * linux /arch/arm/mach-omap2/usb-cywb-pnand.c
+ *
+ * Copyright (C) 2010  Cypress Semiconductor
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/module.h>
+
+#include <plat/gpmc.h>
+
+/*
+ * chip select number on GPMC ( 0..7 )
+ */
+#define AST_GPMC_CS 4
+
+/*
+ * for use by gpmc_set_timings api, measured in ns, not clocks
+ */
+#define WB_GPMC_BUSCYC_t    (7 * 6)
+#define WB_GPMC_CS_t_o_n    (0)
+#define WB_GPMC_ADV_t_o_n   (0)
+#define WB_GPMC_OE_t_o_n    (0)
+#define WB_GPMC_OE_t_o_f_f  (5 * 6)
+#define WB_GPMC_WE_t_o_n    (1 * 6)
+#define WB_GPMC_WE_t_o_f_f  (5 * 6)
+#define WB_GPMC_RDS_ADJ     (2 * 6)
+#define WB_GPMC_RD_t_a_c_c  (WB_GPMC_OE_t_o_f_f + WB_GPMC_RDS_ADJ)
+#define WB_GPMC_WR_t_a_c_c  (WB_GPMC_BUSCYC_t)
+
+#define GPMC_16BIT_MODE 0
+#define GPMC_RETIME     1
+
+/*
+ * GPMC_CONFIG7[cs] register bit fields
+ * AS_CS_MASK - 3 bit mask for  A26,A25,A24,
+ * AS_CS_BADDR - 6 BIT VALUE  A29 ...A24
+ * CSVALID_B - CSVALID bit on GPMC_CONFIG7[cs] register
+ */
+#define AS_CS_MASK	(0X7 << 8)
+#define AS_CS_BADDR	 0x02
+#define CSVALID_B (1 << 6)
+
+#define BLKSZ_4K 0x1000
+
+/*
+ * switch GPMC DATA bus mode
+ */
+void cywb_gpmc_enable_16bit_bus(bool dbus16_enabled)
+{
+	uint32_t tmp32;
+
+	/*
+	 * disable gpmc CS4 operation 1st
+	 */
+	tmp32 = gpmc_cs_read_reg(AST_GPMC_CS,
+				GPMC_CS_CONFIG7) & ~GPMC_CONFIG7_CSVALID;
+	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7, tmp32);
+
+	/*
+	 * GPMC NAND data bus can be 8 or 16 bit wide
+	 */
+	if (dbus16_enabled) {
+		printk(KERN_INFO "enabling 16 bit bus\n");
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
+				(GPMC_CONFIG1_DEVICETYPE(2) |
+				GPMC_CONFIG1_WAIT_PIN_SEL(2) |
+				GPMC_CONFIG1_DEVICESIZE_16)
+				);
+	} else {
+		printk(KERN_INFO "enabling 8 bit bus\n");
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
+				(GPMC_CONFIG1_DEVICETYPE(2) |
+				GPMC_CONFIG1_WAIT_PIN_SEL(2))
+				);
+	}
+
+	/*
+	 * re-enable astoria CS operation on GPMC
+	 */
+	 gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
+			(tmp32 | GPMC_CONFIG7_CSVALID));
+}
+
+int cywb_pnand_platform_retime(int action, bool dbus16_enabled)
+{
+	u32 tmp32;
+	struct gpmc_timings	timings;
+	int retval;
+
+	switch (action) {
+
+	case GPMC_16BIT_MODE:
+		cywb_gpmc_enable_16bit_bus(dbus16_enabled);
+		retval = 0;
+		break;
+	case GPMC_RETIME:
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
+						(GPMC_CONFIG1_DEVICETYPE(2) |
+						GPMC_CONFIG1_WAIT_PIN_SEL(2)));
+
+		memset(&timings, 0, sizeof(timings));
+
+		/* cs timing */
+		timings.cs_on = WB_GPMC_CS_t_o_n;
+		timings.cs_wr_off = WB_GPMC_BUSCYC_t;
+		timings.cs_rd_off = WB_GPMC_BUSCYC_t;
+
+		/* adv timing */
+		timings.adv_on = WB_GPMC_ADV_t_o_n;
+		timings.adv_rd_off = WB_GPMC_BUSCYC_t;
+		timings.adv_wr_off = WB_GPMC_BUSCYC_t;
+
+		/* oe timing */
+		timings.oe_on = WB_GPMC_OE_t_o_n;
+		timings.oe_off = WB_GPMC_OE_t_o_f_f;
+		timings.access = WB_GPMC_RD_t_a_c_c;
+		timings.rd_cycle = WB_GPMC_BUSCYC_t;
+
+		/* we timing */
+		timings.we_on = WB_GPMC_WE_t_o_n;
+		timings.we_off = WB_GPMC_WE_t_o_f_f;
+		timings.wr_access = WB_GPMC_WR_t_a_c_c;
+		timings.wr_cycle = WB_GPMC_BUSCYC_t;
+
+		timings.page_burst_access = WB_GPMC_BUSCYC_t;
+		timings.wr_data_mux_bus = WB_GPMC_BUSCYC_t;
+		gpmc_cs_set_timings(AST_GPMC_CS, &timings);
+
+		/*
+		 * DISABLE cs4, NOTE GPMC REG7 is already configured
+		 * at this point by gpmc_cs_request
+		 */
+		tmp32 = gpmc_cs_read_reg(AST_GPMC_CS, GPMC_CS_CONFIG7) &
+						~GPMC_CONFIG7_CSVALID;
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7, tmp32);
+
+		/*
+		 * PROGRAM chip select Region, (see OMAP3430 TRM PAGE 1088)
+		 */
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
+					(AS_CS_MASK | AS_CS_BADDR));
+
+		/*
+		 * by default configure GPMC into 8 bit mode
+		 * (to match astoria default mode)
+		 */
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
+					(GPMC_CONFIG1_DEVICETYPE(2) |
+					GPMC_CONFIG1_WAIT_PIN_SEL(2)));
+
+		/*
+		 * ENABLE astoria cs operation on GPMC
+		 */
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
+						(tmp32 | GPMC_CONFIG7_CSVALID));
+		retval = 0;
+		break;
+	default:
+		retval = -EINVAL;
+		break;
+	}
+
+	return retval;
+
+}
+EXPORT_SYMBOL(cywb_pnand_platform_retime);
+


---------------------------------------------------------------
This message and any attachments may contain Cypress (or its
subsidiaries) confidential information. If it has been received
in error, please advise the sender and immediately delete this
message.
---------------------------------------------------------------

Re: [PATCH] adding gpmc configuration functions, west bridge related

[Greg KH]

On Wed, Dec 15, 2010 at 11:57:26AM -0800, Sutharsan wrote:
> 
> This patch adds and exports gpmc configuration functions. 
> 'gpmc' configuration functions will be used by westbridge device controller driver.

So this driver isn't submitted yet?

Then I would hold off on this until that time when it is needed by that
other driver.

Also, any USB related patches should be copied to the
linux-usb@vger.kernel.org list, and any ARM patches to that related
list, so next time cc: 2 more lists please.

thanks,

greg k-h

Re: [PATCH] adding gpmc configuration functions, west bridge related

[Sutharsan]

Hi Greg,

The driver is in staging area, the patch I submitted is required to get
the driver out of staging area. This patch is continuation of David
Cross'(odc@cypress.com) earlier patch "[PATCH] gpmc, EXPORT_SYMBOLS,
west bridge related".

I've modified the driver to use the function exported by "[PATCH] adding
gpmc configuration functions, west bridge related". I'll submit the
modified driver as another patch.

Thanks,
Sutharsan.

On Wed, 2010-12-15 at 12:10 -0800, Greg KH wrote:
> On Wed, Dec 15, 2010 at 11:57:26AM -0800, Sutharsan wrote:
> > 
> > This patch adds and exports gpmc configuration functions. 
> > 'gpmc' configuration functions will be used by westbridge device controller driver.
> 
> So this driver isn't submitted yet?
> 
> Then I would hold off on this until that time when it is needed by that
> other driver.
> 
> Also, any USB related patches should be copied to the
> linux-usb@vger.kernel.org list, and any ARM patches to that related
> list, so next time cc: 2 more lists please.
> 
> thanks,
> 
> greg k-h
> 



---------------------------------------------------------------
This message and any attachments may contain Cypress (or its
subsidiaries) confidential information. If it has been received
in error, please advise the sender and immediately delete this
message.
---------------------------------------------------------------

Re: [PATCH] adding gpmc configuration functions, west bridge related

[Greg KH]

A: No.
Q: Should I include quotations after my reply?

http://daringfireball.net/2007/07/on_top

On Wed, Dec 15, 2010 at 02:11:15PM -0800, Sutharsan wrote:
> Hi Greg,
> 
> The driver is in staging area, the patch I submitted is required to get
> the driver out of staging area.

But you didn't say that, the patch you sent was not for the staging
tree, right?

> This patch is continuation of David Cross'(odc@cypress.com) earlier
> patch "[PATCH] gpmc, EXPORT_SYMBOLS, west bridge related".
> 
> I've modified the driver to use the function exported by "[PATCH] adding
> gpmc configuration functions, west bridge related". I'll submit the
> modified driver as another patch.

that would be good, thanks.

greg k-h

Re: [PATCH] adding gpmc configuration functions, west bridge related

[Sutharsan]

On Wed, 2010-12-15 at 14:18 -0800, Greg KH wrote:
> A: No.
> Q: Should I include quotations after my reply?
> 
> http://daringfireball.net/2007/07/on_top
Thanks.
> 
> On Wed, Dec 15, 2010 at 02:11:15PM -0800, Sutharsan wrote:
> > Hi Greg,
> > 
> > The driver is in staging area, the patch I submitted is required to get
> > the driver out of staging area.
> 
> But you didn't say that, the patch you sent was not for the staging
> tree, right?
That's right. 
> 
> > This patch is continuation of David Cross'(odc@cypress.com) earlier
> > patch "[PATCH] gpmc, EXPORT_SYMBOLS, west bridge related".
> > 
> > I've modified the driver to use the function exported by "[PATCH] adding
> > gpmc configuration functions, west bridge related". I'll submit the
> > modified driver as another patch.
> 
> that would be good, thanks.
> 
> greg k-h
> 



---------------------------------------------------------------
This message and any attachments may contain Cypress (or its
subsidiaries) confidential information. If it has been received
in error, please advise the sender and immediately delete this
message.
---------------------------------------------------------------

[PATCH] adding gpmc configuration functions, west bridge related

[Sutharsan]

This patch adds and exports gpmc configuration functions.
'gpmc' configuration functions will be used by 
westbridge device controller driver in staging tree.
This patch is required to get westbridge device controller driver 
out of staging tree.

Signed-off-by: Sutharsan Ramamoorthy <srmt@cypress.com>
---

diff -uprN -X linux-2.6.37_vanilla/Documentation/dontdiff linux-2.6.37_vanilla/arch/arm/mach-omap2/Makefile linux-2.6.37-cywb/arch/arm/mach-omap2/Makefile
--- linux-2.6.37_vanilla/arch/arm/mach-omap2/Makefile	2010-11-29 20:42:04.000000000 -0800
+++ linux-2.6.37-cywb/arch/arm/mach-omap2/Makefile	2010-12-13 16:04:08.378446603 -0800
@@ -182,6 +182,7 @@ obj-y					+= $(usbfs-m) $(usbfs-y)
 obj-y					+= usb-musb.o
 obj-$(CONFIG_MACH_OMAP2_TUSB6010)	+= usb-tusb6010.o
 obj-y					+= usb-ehci.o
+obj-$(CONFIG_WESTBRIDGE_ASTORIA)        += usb-cywb-pnand.o
 
 onenand-$(CONFIG_MTD_ONENAND_OMAP2)	:= gpmc-onenand.o
 obj-y					+= $(onenand-m) $(onenand-y)
diff -uprN -X linux-2.6.37_vanilla/Documentation/dontdiff linux-2.6.37_vanilla/arch/arm/mach-omap2/usb-cywb-pnand.c linux-2.6.37-cywb/arch/arm/mach-omap2/usb-cywb-pnand.c
--- linux-2.6.37_vanilla/arch/arm/mach-omap2/usb-cywb-pnand.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-2.6.37-cywb/arch/arm/mach-omap2/usb-cywb-pnand.c	2010-12-14 15:51:13.710787480 -0800
@@ -0,0 +1,182 @@
+/*
+ * linux /arch/arm/mach-omap2/usb-cywb-pnand.c
+ *
+ * Copyright (C) 2010  Cypress Semiconductor
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/module.h>
+
+#include <plat/gpmc.h>
+
+/*
+ * chip select number on GPMC ( 0..7 )
+ */
+#define AST_GPMC_CS 4
+
+/*
+ * for use by gpmc_set_timings api, measured in ns, not clocks
+ */
+#define WB_GPMC_BUSCYC_t    (7 * 6)
+#define WB_GPMC_CS_t_o_n    (0)
+#define WB_GPMC_ADV_t_o_n   (0)
+#define WB_GPMC_OE_t_o_n    (0)
+#define WB_GPMC_OE_t_o_f_f  (5 * 6)
+#define WB_GPMC_WE_t_o_n    (1 * 6)
+#define WB_GPMC_WE_t_o_f_f  (5 * 6)
+#define WB_GPMC_RDS_ADJ     (2 * 6)
+#define WB_GPMC_RD_t_a_c_c  (WB_GPMC_OE_t_o_f_f + WB_GPMC_RDS_ADJ)
+#define WB_GPMC_WR_t_a_c_c  (WB_GPMC_BUSCYC_t)
+
+#define GPMC_16BIT_MODE 0
+#define GPMC_RETIME     1
+
+/*
+ * GPMC_CONFIG7[cs] register bit fields
+ * AS_CS_MASK - 3 bit mask for  A26,A25,A24,
+ * AS_CS_BADDR - 6 BIT VALUE  A29 ...A24
+ * CSVALID_B - CSVALID bit on GPMC_CONFIG7[cs] register
+ */
+#define AS_CS_MASK	(0X7 << 8)
+#define AS_CS_BADDR	 0x02
+#define CSVALID_B (1 << 6)
+
+#define BLKSZ_4K 0x1000
+
+/*
+ * switch GPMC DATA bus mode
+ */
+void cywb_gpmc_enable_16bit_bus(bool dbus16_enabled)
+{
+	uint32_t tmp32;
+
+	/*
+	 * disable gpmc CS4 operation 1st
+	 */
+	tmp32 = gpmc_cs_read_reg(AST_GPMC_CS,
+				GPMC_CS_CONFIG7) & ~GPMC_CONFIG7_CSVALID;
+	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7, tmp32);
+
+	/*
+	 * GPMC NAND data bus can be 8 or 16 bit wide
+	 */
+	if (dbus16_enabled) {
+		printk(KERN_INFO "enabling 16 bit bus\n");
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
+				(GPMC_CONFIG1_DEVICETYPE(2) |
+				GPMC_CONFIG1_WAIT_PIN_SEL(2) |
+				GPMC_CONFIG1_DEVICESIZE_16)
+				);
+	} else {
+		printk(KERN_INFO "enabling 8 bit bus\n");
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
+				(GPMC_CONFIG1_DEVICETYPE(2) |
+				GPMC_CONFIG1_WAIT_PIN_SEL(2))
+				);
+	}
+
+	/*
+	 * re-enable astoria CS operation on GPMC
+	 */
+	 gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
+			(tmp32 | GPMC_CONFIG7_CSVALID));
+}
+
+int cywb_pnand_platform_retime(int action, bool dbus16_enabled)
+{
+	u32 tmp32;
+	struct gpmc_timings	timings;
+	int retval;
+
+	switch (action) {
+
+	case GPMC_16BIT_MODE:
+		cywb_gpmc_enable_16bit_bus(dbus16_enabled);
+		retval = 0;
+		break;
+	case GPMC_RETIME:
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
+						(GPMC_CONFIG1_DEVICETYPE(2) |
+						GPMC_CONFIG1_WAIT_PIN_SEL(2)));
+
+		memset(&timings, 0, sizeof(timings));
+
+		/* cs timing */
+		timings.cs_on = WB_GPMC_CS_t_o_n;
+		timings.cs_wr_off = WB_GPMC_BUSCYC_t;
+		timings.cs_rd_off = WB_GPMC_BUSCYC_t;
+
+		/* adv timing */
+		timings.adv_on = WB_GPMC_ADV_t_o_n;
+		timings.adv_rd_off = WB_GPMC_BUSCYC_t;
+		timings.adv_wr_off = WB_GPMC_BUSCYC_t;
+
+		/* oe timing */
+		timings.oe_on = WB_GPMC_OE_t_o_n;
+		timings.oe_off = WB_GPMC_OE_t_o_f_f;
+		timings.access = WB_GPMC_RD_t_a_c_c;
+		timings.rd_cycle = WB_GPMC_BUSCYC_t;
+
+		/* we timing */
+		timings.we_on = WB_GPMC_WE_t_o_n;
+		timings.we_off = WB_GPMC_WE_t_o_f_f;
+		timings.wr_access = WB_GPMC_WR_t_a_c_c;
+		timings.wr_cycle = WB_GPMC_BUSCYC_t;
+
+		timings.page_burst_access = WB_GPMC_BUSCYC_t;
+		timings.wr_data_mux_bus = WB_GPMC_BUSCYC_t;
+		gpmc_cs_set_timings(AST_GPMC_CS, &timings);
+
+		/*
+		 * DISABLE cs4, NOTE GPMC REG7 is already configured
+		 * at this point by gpmc_cs_request
+		 */
+		tmp32 = gpmc_cs_read_reg(AST_GPMC_CS, GPMC_CS_CONFIG7) &
+						~GPMC_CONFIG7_CSVALID;
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7, tmp32);
+
+		/*
+		 * PROGRAM chip select Region, (see OMAP3430 TRM PAGE 1088)
+		 */
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
+					(AS_CS_MASK | AS_CS_BADDR));
+
+		/*
+		 * by default configure GPMC into 8 bit mode
+		 * (to match astoria default mode)
+		 */
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
+					(GPMC_CONFIG1_DEVICETYPE(2) |
+					GPMC_CONFIG1_WAIT_PIN_SEL(2)));
+
+		/*
+		 * ENABLE astoria cs operation on GPMC
+		 */
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
+						(tmp32 | GPMC_CONFIG7_CSVALID));
+		retval = 0;
+		break;
+	default:
+		retval = -EINVAL;
+		break;
+	}
+
+	return retval;
+
+}
+EXPORT_SYMBOL(cywb_pnand_platform_retime);
+


---------------------------------------------------------------
This message and any attachments may contain Cypress (or its
subsidiaries) confidential information. If it has been received
in error, please advise the sender and immediately delete this
message.
---------------------------------------------------------------

Re: [PATCH] adding gpmc configuration functions, west bridge related

[Greg KH]

On Thu, Dec 16, 2010 at 04:33:50PM -0800, Sutharsan wrote:
> 
> This patch adds and exports gpmc configuration functions.
> 'gpmc' configuration functions will be used by 
> westbridge device controller driver in staging tree.
> This patch is required to get westbridge device controller driver 
> out of staging tree.

Well, it's one step to getting the code out, not the only thing :)

> Signed-off-by: Sutharsan Ramamoorthy <srmt@cypress.com>
> ---
> 
> diff -uprN -X linux-2.6.37_vanilla/Documentation/dontdiff linux-2.6.37_vanilla/arch/arm/mach-omap2/Makefile linux-2.6.37-cywb/arch/arm/mach-omap2/Makefile
> --- linux-2.6.37_vanilla/arch/arm/mach-omap2/Makefile	2010-11-29 20:42:04.000000000 -0800
> +++ linux-2.6.37-cywb/arch/arm/mach-omap2/Makefile	2010-12-13 16:04:08.378446603 -0800
> @@ -182,6 +182,7 @@ obj-y					+= $(usbfs-m) $(usbfs-y)
>  obj-y					+= usb-musb.o
>  obj-$(CONFIG_MACH_OMAP2_TUSB6010)	+= usb-tusb6010.o
>  obj-y					+= usb-ehci.o
> +obj-$(CONFIG_WESTBRIDGE_ASTORIA)        += usb-cywb-pnand.o
>  
>  onenand-$(CONFIG_MTD_ONENAND_OMAP2)	:= gpmc-onenand.o
>  obj-y					+= $(onenand-m) $(onenand-y)
> diff -uprN -X linux-2.6.37_vanilla/Documentation/dontdiff linux-2.6.37_vanilla/arch/arm/mach-omap2/usb-cywb-pnand.c linux-2.6.37-cywb/arch/arm/mach-omap2/usb-cywb-pnand.c
> --- linux-2.6.37_vanilla/arch/arm/mach-omap2/usb-cywb-pnand.c	1969-12-31 16:00:00.000000000 -0800
> +++ linux-2.6.37-cywb/arch/arm/mach-omap2/usb-cywb-pnand.c	2010-12-14 15:51:13.710787480 -0800
> @@ -0,0 +1,182 @@
> +/*
> + * linux /arch/arm/mach-omap2/usb-cywb-pnand.c
> + *
> + * Copyright (C) 2010  Cypress Semiconductor
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.

Do you _really_ mean "any later version"?  Are you aware of the issues
involved here?

> +
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> +
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor,
> + * Boston, MA  02110-1301, USA.

These two paragraphs are not needed.

> + */
> +
> +#include <linux/module.h>
> +
> +#include <plat/gpmc.h>
> +
> +/*
> + * chip select number on GPMC ( 0..7 )
> + */
> +#define AST_GPMC_CS 4
> +
> +/*
> + * for use by gpmc_set_timings api, measured in ns, not clocks
> + */
> +#define WB_GPMC_BUSCYC_t    (7 * 6)
> +#define WB_GPMC_CS_t_o_n    (0)
> +#define WB_GPMC_ADV_t_o_n   (0)
> +#define WB_GPMC_OE_t_o_n    (0)
> +#define WB_GPMC_OE_t_o_f_f  (5 * 6)
> +#define WB_GPMC_WE_t_o_n    (1 * 6)
> +#define WB_GPMC_WE_t_o_f_f  (5 * 6)
> +#define WB_GPMC_RDS_ADJ     (2 * 6)
> +#define WB_GPMC_RD_t_a_c_c  (WB_GPMC_OE_t_o_f_f + WB_GPMC_RDS_ADJ)
> +#define WB_GPMC_WR_t_a_c_c  (WB_GPMC_BUSCYC_t)
> +
> +#define GPMC_16BIT_MODE 0
> +#define GPMC_RETIME     1
> +
> +/*
> + * GPMC_CONFIG7[cs] register bit fields
> + * AS_CS_MASK - 3 bit mask for  A26,A25,A24,
> + * AS_CS_BADDR - 6 BIT VALUE  A29 ...A24
> + * CSVALID_B - CSVALID bit on GPMC_CONFIG7[cs] register
> + */
> +#define AS_CS_MASK	(0X7 << 8)
> +#define AS_CS_BADDR	 0x02
> +#define CSVALID_B (1 << 6)
> +
> +#define BLKSZ_4K 0x1000
> +
> +/*
> + * switch GPMC DATA bus mode
> + */
> +void cywb_gpmc_enable_16bit_bus(bool dbus16_enabled)
> +{
> +	uint32_t tmp32;

Ick, please use the "real" types for the kernel (u32 in this case.)

> +
> +	/*
> +	 * disable gpmc CS4 operation 1st
> +	 */
> +	tmp32 = gpmc_cs_read_reg(AST_GPMC_CS,
> +				GPMC_CS_CONFIG7) & ~GPMC_CONFIG7_CSVALID;
> +	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7, tmp32);
> +
> +	/*
> +	 * GPMC NAND data bus can be 8 or 16 bit wide
> +	 */
> +	if (dbus16_enabled) {
> +		printk(KERN_INFO "enabling 16 bit bus\n");

Why print this for the whole world to see?  Also, no prefix saying
exactly what code is printing this out?  Is this even needed?

> +		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
> +				(GPMC_CONFIG1_DEVICETYPE(2) |
> +				GPMC_CONFIG1_WAIT_PIN_SEL(2) |
> +				GPMC_CONFIG1_DEVICESIZE_16)
> +				);

Odd place to put a trailing ')' character.

> +	} else {
> +		printk(KERN_INFO "enabling 8 bit bus\n");

Same as above.

> +		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
> +				(GPMC_CONFIG1_DEVICETYPE(2) |
> +				GPMC_CONFIG1_WAIT_PIN_SEL(2))
> +				);

Samehere.

> +	}
> +
> +	/*
> +	 * re-enable astoria CS operation on GPMC
> +	 */
> +	 gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
> +			(tmp32 | GPMC_CONFIG7_CSVALID));
> +}
> +
> +int cywb_pnand_platform_retime(int action, bool dbus16_enabled)
> +{
> +	u32 tmp32;

See, you got it right here :)

> +	struct gpmc_timings	timings;

What's with the extra padding?

> +	int retval;
> +
> +	switch (action) {
> +
> +	case GPMC_16BIT_MODE:
> +		cywb_gpmc_enable_16bit_bus(dbus16_enabled);
> +		retval = 0;
> +		break;
> +	case GPMC_RETIME:
> +		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
> +						(GPMC_CONFIG1_DEVICETYPE(2) |
> +						GPMC_CONFIG1_WAIT_PIN_SEL(2)));
> +
> +		memset(&timings, 0, sizeof(timings));
> +
> +		/* cs timing */
> +		timings.cs_on = WB_GPMC_CS_t_o_n;
> +		timings.cs_wr_off = WB_GPMC_BUSCYC_t;
> +		timings.cs_rd_off = WB_GPMC_BUSCYC_t;
> +
> +		/* adv timing */
> +		timings.adv_on = WB_GPMC_ADV_t_o_n;
> +		timings.adv_rd_off = WB_GPMC_BUSCYC_t;
> +		timings.adv_wr_off = WB_GPMC_BUSCYC_t;
> +
> +		/* oe timing */
> +		timings.oe_on = WB_GPMC_OE_t_o_n;
> +		timings.oe_off = WB_GPMC_OE_t_o_f_f;
> +		timings.access = WB_GPMC_RD_t_a_c_c;
> +		timings.rd_cycle = WB_GPMC_BUSCYC_t;
> +
> +		/* we timing */
> +		timings.we_on = WB_GPMC_WE_t_o_n;
> +		timings.we_off = WB_GPMC_WE_t_o_f_f;
> +		timings.wr_access = WB_GPMC_WR_t_a_c_c;
> +		timings.wr_cycle = WB_GPMC_BUSCYC_t;
> +
> +		timings.page_burst_access = WB_GPMC_BUSCYC_t;
> +		timings.wr_data_mux_bus = WB_GPMC_BUSCYC_t;
> +		gpmc_cs_set_timings(AST_GPMC_CS, &timings);
> +
> +		/*
> +		 * DISABLE cs4, NOTE GPMC REG7 is already configured
> +		 * at this point by gpmc_cs_request
> +		 */
> +		tmp32 = gpmc_cs_read_reg(AST_GPMC_CS, GPMC_CS_CONFIG7) &
> +						~GPMC_CONFIG7_CSVALID;
> +		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7, tmp32);
> +
> +		/*
> +		 * PROGRAM chip select Region, (see OMAP3430 TRM PAGE 1088)
> +		 */
> +		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
> +					(AS_CS_MASK | AS_CS_BADDR));
> +
> +		/*
> +		 * by default configure GPMC into 8 bit mode
> +		 * (to match astoria default mode)
> +		 */
> +		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
> +					(GPMC_CONFIG1_DEVICETYPE(2) |
> +					GPMC_CONFIG1_WAIT_PIN_SEL(2)));
> +
> +		/*
> +		 * ENABLE astoria cs operation on GPMC
> +		 */
> +		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
> +						(tmp32 | GPMC_CONFIG7_CSVALID));
> +		retval = 0;
> +		break;
> +	default:
> +		retval = -EINVAL;
> +		break;
> +	}
> +
> +	return retval;
> +
> +}
> +EXPORT_SYMBOL(cywb_pnand_platform_retime);

EXPORT_SYMBOL_GPL()?

> ---------------------------------------------------------------
> This message and any attachments may contain Cypress (or its
> subsidiaries) confidential information. If it has been received
> in error, please advise the sender and immediately delete this
> message.

Please never have this header on any code you have submitted for
inclusion to the Linux kernel, as it is not acceptable, and can be seen
as something that implies you should not be sending this information to
us.

thanks,

greg k-h

[PATCH] adding gpmc configuration functions, west bridge related

[Sutharsan R]

This patch adds and exports gpmc configuration functions.
'gpmc' configuration functions will be used by
westbridge device controller driver in staging tree.
This patch is part of the work to get westbridge device controller driver
out of staging tree.

Signed-off-by: Sutharsan Ramamoorthy <srmt@cypress.com>

---

diff -uprN -X linux-2.6.37_vanilla/Documentation/dontdiff
linux-2.6.37_vanilla/arch/arm/mach-omap2/Makefile
linux-2.6.37-cywb/arch/arm/mach-omap2/Makefile
--- linux-2.6.37_vanilla/arch/arm/mach-omap2/Makefile	2010-11-29
20:42:04.000000000 -0800
+++ linux-2.6.37-cywb/arch/arm/mach-omap2/Makefile	2010-12-13
16:04:08.378446603 -0800
@@ -182,6 +182,7 @@ obj-y					+= $(usbfs-m) $(usbfs-y)
 obj-y					+= usb-musb.o
 obj-$(CONFIG_MACH_OMAP2_TUSB6010)	+= usb-tusb6010.o
 obj-y					+= usb-ehci.o
+obj-$(CONFIG_WESTBRIDGE_ASTORIA)        += usb-cywb-pnand.o

 onenand-$(CONFIG_MTD_ONENAND_OMAP2)	:= gpmc-onenand.o
 obj-y					+= $(onenand-m) $(onenand-y)
diff -uprN -X linux-2.6.37_vanilla/Documentation/dontdiff
linux-2.6.37_vanilla/arch/arm/mach-omap2/usb-cywb-pnand.c
linux-2.6.37-cywb/arch/arm/mach-omap2/usb-cywb-pnand.c
--- linux-2.6.37_vanilla/arch/arm/mach-omap2/usb-cywb-pnand.c	1969-12-31
16:00:00.000000000 -0800
+++ linux-2.6.37-cywb/arch/arm/mach-omap2/usb-cywb-pnand.c	2010-12-20
17:33:23.822251855 -0800
@@ -0,0 +1,170 @@
+/*
+ * linux /arch/arm/mach-omap2/usb-cywb-pnand.c
+ *
+ * Copyright (C) 2010  Cypress Semiconductor
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License.
+ */
+
+#include <linux/module.h>
+
+#include <plat/gpmc.h>
+
+/*
+ * chip select number on GPMC ( 0..7 )
+ */
+#define AST_GPMC_CS 4
+
+/*
+ * for use by gpmc_set_timings api, measured in ns, not clocks
+ */
+#define WB_GPMC_BUSCYC_t    (7 * 6)
+#define WB_GPMC_CS_t_o_n    (0)
+#define WB_GPMC_ADV_t_o_n   (0)
+#define WB_GPMC_OE_t_o_n    (0)
+#define WB_GPMC_OE_t_o_f_f  (5 * 6)
+#define WB_GPMC_WE_t_o_n    (1 * 6)
+#define WB_GPMC_WE_t_o_f_f  (5 * 6)
+#define WB_GPMC_RDS_ADJ     (2 * 6)
+#define WB_GPMC_RD_t_a_c_c  (WB_GPMC_OE_t_o_f_f + WB_GPMC_RDS_ADJ)
+#define WB_GPMC_WR_t_a_c_c  (WB_GPMC_BUSCYC_t)
+
+#define GPMC_16BIT_MODE 0
+#define GPMC_RETIME     1
+
+/*
+ * GPMC_CONFIG7[cs] register bit fields
+ * AS_CS_MASK - 3 bit mask for  A26,A25,A24,
+ * AS_CS_BADDR - 6 BIT VALUE  A29 ...A24
+ * CSVALID_B - CSVALID bit on GPMC_CONFIG7[cs] register
+ */
+#define AS_CS_MASK	(0X7 << 8)
+#define AS_CS_BADDR	 0x02
+#define CSVALID_B (1 << 6)
+
+#define BLKSZ_4K 0x1000
+
+/*
+ * switch GPMC DATA bus mode
+ */
+void cywb_gpmc_enable_16bit_bus(bool dbus16_enabled)
+{
+	u32 tmp32;
+
+	/*
+	 * disable gpmc CS4 operation 1st
+	 */
+	tmp32 = gpmc_cs_read_reg(AST_GPMC_CS,
+				GPMC_CS_CONFIG7) & ~GPMC_CONFIG7_CSVALID;
+	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7, tmp32);
+
+	/*
+	 * GPMC NAND data bus can be 8 or 16 bit wide
+	 */
+	if (dbus16_enabled) {
+		dev_dbg(KERN_INFO "gpmc: enabling 16 bit bus\n");
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
+				(GPMC_CONFIG1_DEVICETYPE(2) |
+				GPMC_CONFIG1_WAIT_PIN_SEL(2) |
+				GPMC_CONFIG1_DEVICESIZE_16));
+	} else {
+		dev_dbg(KERN_INFO "gpmc: enabling 8 bit bus\n");
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
+				(GPMC_CONFIG1_DEVICETYPE(2) |
+				GPMC_CONFIG1_WAIT_PIN_SEL(2)));
+	}
+
+	/*
+	 * re-enable astoria CS operation on GPMC
+	 */
+	 gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
+			(tmp32 | GPMC_CONFIG7_CSVALID));
+}
+
+int cywb_pnand_platform_retime(int action, bool dbus16_enabled)
+{
+	u32 tmp32;
+	struct gpmc_timings timings;
+	int retval;
+
+	switch (action) {
+
+	case GPMC_16BIT_MODE:
+		cywb_gpmc_enable_16bit_bus(dbus16_enabled);
+		retval = 0;
+		break;
+	case GPMC_RETIME:
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
+						(GPMC_CONFIG1_DEVICETYPE(2) |
+						GPMC_CONFIG1_WAIT_PIN_SEL(2)));
+
+		memset(&timings, 0, sizeof(timings));
+
+		/* cs timing */
+		timings.cs_on = WB_GPMC_CS_t_o_n;
+		timings.cs_wr_off = WB_GPMC_BUSCYC_t;
+		timings.cs_rd_off = WB_GPMC_BUSCYC_t;
+
+		/* adv timing */
+		timings.adv_on = WB_GPMC_ADV_t_o_n;
+		timings.adv_rd_off = WB_GPMC_BUSCYC_t;
+		timings.adv_wr_off = WB_GPMC_BUSCYC_t;
+
+		/* oe timing */
+		timings.oe_on = WB_GPMC_OE_t_o_n;
+		timings.oe_off = WB_GPMC_OE_t_o_f_f;
+		timings.access = WB_GPMC_RD_t_a_c_c;
+		timings.rd_cycle = WB_GPMC_BUSCYC_t;
+
+		/* we timing */
+		timings.we_on = WB_GPMC_WE_t_o_n;
+		timings.we_off = WB_GPMC_WE_t_o_f_f;
+		timings.wr_access = WB_GPMC_WR_t_a_c_c;
+		timings.wr_cycle = WB_GPMC_BUSCYC_t;
+
+		timings.page_burst_access = WB_GPMC_BUSCYC_t;
+		timings.wr_data_mux_bus = WB_GPMC_BUSCYC_t;
+		gpmc_cs_set_timings(AST_GPMC_CS, &timings);
+
+		/*
+		 * DISABLE cs4, NOTE GPMC REG7 is already configured
+		 * at this point by gpmc_cs_request
+		 */
+		tmp32 = gpmc_cs_read_reg(AST_GPMC_CS, GPMC_CS_CONFIG7) &
+						~GPMC_CONFIG7_CSVALID;
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7, tmp32);
+
+		/*
+		 * PROGRAM chip select Region, (see OMAP3430 TRM PAGE 1088)
+		 */
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
+					(AS_CS_MASK | AS_CS_BADDR));
+
+		/*
+		 * by default configure GPMC into 8 bit mode
+		 * (to match astoria default mode)
+		 */
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
+					(GPMC_CONFIG1_DEVICETYPE(2) |
+					GPMC_CONFIG1_WAIT_PIN_SEL(2)));
+
+		/*
+		 * ENABLE astoria cs operation on GPMC
+		 */
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
+						(tmp32 | GPMC_CONFIG7_CSVALID));
+		retval = 0;
+		break;
+	default:
+		retval = -EINVAL;
+		break;
+	}
+
+	return retval;
+
+}
+EXPORT_SYMBOL(cywb_pnand_platform_retime);
+

Re: [PATCH] adding gpmc configuration functions, west bridge related

[Greg KH]

On Mon, Dec 20, 2010 at 06:42:06PM -0800, Sutharsan R wrote:
> This patch adds and exports gpmc configuration functions.
> 'gpmc' configuration functions will be used by
> westbridge device controller driver in staging tree.
> This patch is part of the work to get westbridge device controller driver
> out of staging tree.
> 
> Signed-off-by: Sutharsan Ramamoorthy <srmt@cypress.com>
> 
> ---
> 
> diff -uprN -X linux-2.6.37_vanilla/Documentation/dontdiff
> linux-2.6.37_vanilla/arch/arm/mach-omap2/Makefile
> linux-2.6.37-cywb/arch/arm/mach-omap2/Makefile
> --- linux-2.6.37_vanilla/arch/arm/mach-omap2/Makefile	2010-11-29
> 20:42:04.000000000 -0800
> +++ linux-2.6.37-cywb/arch/arm/mach-omap2/Makefile	2010-12-13
> 16:04:08.378446603 -0800

Your patch is linewrapped :(

> @@ -182,6 +182,7 @@ obj-y					+= $(usbfs-m) $(usbfs-y)
>  obj-y					+= usb-musb.o
>  obj-$(CONFIG_MACH_OMAP2_TUSB6010)	+= usb-tusb6010.o
>  obj-y					+= usb-ehci.o
> +obj-$(CONFIG_WESTBRIDGE_ASTORIA)        += usb-cywb-pnand.o
> 
>  onenand-$(CONFIG_MTD_ONENAND_OMAP2)	:= gpmc-onenand.o
>  obj-y					+= $(onenand-m) $(onenand-y)
> diff -uprN -X linux-2.6.37_vanilla/Documentation/dontdiff
> linux-2.6.37_vanilla/arch/arm/mach-omap2/usb-cywb-pnand.c
> linux-2.6.37-cywb/arch/arm/mach-omap2/usb-cywb-pnand.c
> --- linux-2.6.37_vanilla/arch/arm/mach-omap2/usb-cywb-pnand.c	1969-12-31
> 16:00:00.000000000 -0800
> +++ linux-2.6.37-cywb/arch/arm/mach-omap2/usb-cywb-pnand.c	2010-12-20
> 17:33:23.822251855 -0800
> @@ -0,0 +1,170 @@
> +/*
> + * linux /arch/arm/mach-omap2/usb-cywb-pnand.c
> + *
> + * Copyright (C) 2010  Cypress Semiconductor
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License.

Either, or what?

> + */
> +
> +#include <linux/module.h>
> +
> +#include <plat/gpmc.h>

Why the extra lines inbetween the #includes?

> +
> +/*
> + * chip select number on GPMC ( 0..7 )
> + */
> +#define AST_GPMC_CS 4
> +
> +/*
> + * for use by gpmc_set_timings api, measured in ns, not clocks
> + */
> +#define WB_GPMC_BUSCYC_t    (7 * 6)

What's with the lowercase values in #defines?

> +#define WB_GPMC_CS_t_o_n    (0)
> +#define WB_GPMC_ADV_t_o_n   (0)
> +#define WB_GPMC_OE_t_o_n    (0)
> +#define WB_GPMC_OE_t_o_f_f  (5 * 6)
> +#define WB_GPMC_WE_t_o_n    (1 * 6)
> +#define WB_GPMC_WE_t_o_f_f  (5 * 6)
> +#define WB_GPMC_RDS_ADJ     (2 * 6)
> +#define WB_GPMC_RD_t_a_c_c  (WB_GPMC_OE_t_o_f_f + WB_GPMC_RDS_ADJ)
> +#define WB_GPMC_WR_t_a_c_c  (WB_GPMC_BUSCYC_t)
> +
> +#define GPMC_16BIT_MODE 0
> +#define GPMC_RETIME     1
> +
> +/*
> + * GPMC_CONFIG7[cs] register bit fields
> + * AS_CS_MASK - 3 bit mask for  A26,A25,A24,
> + * AS_CS_BADDR - 6 BIT VALUE  A29 ...A24
> + * CSVALID_B - CSVALID bit on GPMC_CONFIG7[cs] register
> + */
> +#define AS_CS_MASK	(0X7 << 8)
> +#define AS_CS_BADDR	 0x02
> +#define CSVALID_B (1 << 6)
> +
> +#define BLKSZ_4K 0x1000
> +
> +/*
> + * switch GPMC DATA bus mode
> + */
> +void cywb_gpmc_enable_16bit_bus(bool dbus16_enabled)
> +{
> +	u32 tmp32;
> +
> +	/*
> +	 * disable gpmc CS4 operation 1st
> +	 */
> +	tmp32 = gpmc_cs_read_reg(AST_GPMC_CS,
> +				GPMC_CS_CONFIG7) & ~GPMC_CONFIG7_CSVALID;
> +	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7, tmp32);
> +
> +	/*
> +	 * GPMC NAND data bus can be 8 or 16 bit wide
> +	 */
> +	if (dbus16_enabled) {
> +		dev_dbg(KERN_INFO "gpmc: enabling 16 bit bus\n");
> +		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
> +				(GPMC_CONFIG1_DEVICETYPE(2) |
> +				GPMC_CONFIG1_WAIT_PIN_SEL(2) |
> +				GPMC_CONFIG1_DEVICESIZE_16));
> +	} else {
> +		dev_dbg(KERN_INFO "gpmc: enabling 8 bit bus\n");
> +		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
> +				(GPMC_CONFIG1_DEVICETYPE(2) |
> +				GPMC_CONFIG1_WAIT_PIN_SEL(2)));
> +	}
> +
> +	/*
> +	 * re-enable astoria CS operation on GPMC
> +	 */
> +	 gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
> +			(tmp32 | GPMC_CONFIG7_CSVALID));
> +}
> +
> +int cywb_pnand_platform_retime(int action, bool dbus16_enabled)
> +{
> +	u32 tmp32;
> +	struct gpmc_timings timings;
> +	int retval;

Set retval to 0 first, then you don't have to set it for when things go
right, only when things go wrong.

> +
> +	switch (action) {
> +
> +	case GPMC_16BIT_MODE:
> +		cywb_gpmc_enable_16bit_bus(dbus16_enabled);
> +		retval = 0;
> +		break;
> +	case GPMC_RETIME:
> +		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
> +						(GPMC_CONFIG1_DEVICETYPE(2) |
> +						GPMC_CONFIG1_WAIT_PIN_SEL(2)));
> +
> +		memset(&timings, 0, sizeof(timings));
> +
> +		/* cs timing */
> +		timings.cs_on = WB_GPMC_CS_t_o_n;
> +		timings.cs_wr_off = WB_GPMC_BUSCYC_t;
> +		timings.cs_rd_off = WB_GPMC_BUSCYC_t;
> +
> +		/* adv timing */
> +		timings.adv_on = WB_GPMC_ADV_t_o_n;
> +		timings.adv_rd_off = WB_GPMC_BUSCYC_t;
> +		timings.adv_wr_off = WB_GPMC_BUSCYC_t;
> +
> +		/* oe timing */
> +		timings.oe_on = WB_GPMC_OE_t_o_n;
> +		timings.oe_off = WB_GPMC_OE_t_o_f_f;
> +		timings.access = WB_GPMC_RD_t_a_c_c;
> +		timings.rd_cycle = WB_GPMC_BUSCYC_t;
> +
> +		/* we timing */
> +		timings.we_on = WB_GPMC_WE_t_o_n;
> +		timings.we_off = WB_GPMC_WE_t_o_f_f;
> +		timings.wr_access = WB_GPMC_WR_t_a_c_c;
> +		timings.wr_cycle = WB_GPMC_BUSCYC_t;
> +
> +		timings.page_burst_access = WB_GPMC_BUSCYC_t;
> +		timings.wr_data_mux_bus = WB_GPMC_BUSCYC_t;
> +		gpmc_cs_set_timings(AST_GPMC_CS, &timings);
> +
> +		/*
> +		 * DISABLE cs4, NOTE GPMC REG7 is already configured
> +		 * at this point by gpmc_cs_request
> +		 */
> +		tmp32 = gpmc_cs_read_reg(AST_GPMC_CS, GPMC_CS_CONFIG7) &
> +						~GPMC_CONFIG7_CSVALID;
> +		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7, tmp32);
> +
> +		/*
> +		 * PROGRAM chip select Region, (see OMAP3430 TRM PAGE 1088)
> +		 */
> +		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
> +					(AS_CS_MASK | AS_CS_BADDR));
> +
> +		/*
> +		 * by default configure GPMC into 8 bit mode
> +		 * (to match astoria default mode)
> +		 */
> +		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
> +					(GPMC_CONFIG1_DEVICETYPE(2) |
> +					GPMC_CONFIG1_WAIT_PIN_SEL(2)));
> +
> +		/*
> +		 * ENABLE astoria cs operation on GPMC
> +		 */
> +		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
> +						(tmp32 | GPMC_CONFIG7_CSVALID));
> +		retval = 0;
> +		break;
> +	default:
> +		retval = -EINVAL;

No error message?  How could this ever happen?

> +		break;
> +	}
> +
> +	return retval;
> +
> +}
> +EXPORT_SYMBOL(cywb_pnand_platform_retime);

Again, are you sure about this export?

What code uses this?  If it is the staging driver, is this code now
duplicated there?  If so, why not remove it in the same patch, that
would make more sense.

Also, the code above will break the build, you obviously never even
tested it out.  Why would you send us something and expect us to apply
it, when you did not do the most simplest of tests yourself?

{sigh}

greg k-h

Re: [PATCH] adding gpmc configuration functions, west bridge related

[Tony Lindgren]

* Sutharsan R <sutharsan.ram@gmail.com> [101220 18:41]:
> This patch adds and exports gpmc configuration functions.
> 'gpmc' configuration functions will be used by
> westbridge device controller driver in staging tree.
> This patch is part of the work to get westbridge device controller driver
> out of staging tree.

Looks good in general..

> +EXPORT_SYMBOL(cywb_pnand_platform_retime);

But this you should not need. I know tusb6010 is
still doing that, but you can pass it in the platform_data
and then there's no need to export it.

Then in your driver you can do:

if (xxxxx->retime)
	xxxxx->retime(123);

That way the driver will stay generic. The set_power
functions are doing that in drivers/usb/musb if you
need examples.

Also, this will need a slight update based on Adrian Hunter's
patch "OMAP2/3: GPMC: put sync_clk value in picoseconds
instead of nanosecond" that I'll be queuing.

Regards,

Tony

Re: [PATCH] adding gpmc configuration functions, west bridge related

[Greg KH]

On Wed, Jan 12, 2011 at 12:56:44PM -0800, Sutharsan Ramamoorthy wrote:
> This patch implements gpmc configuration functions.

Why?

> These gpmc functions are used by westbridge device controller driver
> in staging tree to configure gpmc timings and bus width.

How does the driver live today without these functions?

And as this is a staging driver, any way to just leave the functions in
the staging driver for now, as there are lots of other things that need
to be done to this driver before it can be moved out of the staging
tree.

Or is this one of those things?

> This patch has been compiled in linux-2.6.37-rc4

This line isn't needed.

You also forgot the line:
	This patch is corrupted by my email client and can not be
	applied or built properly.
:(

> New files:
> 1. ../arch/arm/mach-omap2/usb-cywb-pnand.c
> 2. ../include/linux/usb/cywb.h
> 
> Modified files:
> 1. ../arch/arm/mach-omap2/board-zoom-peripherals.c
> 2. ../arch/arm/mach-omap2/Makefile
> 3.
> ../drivers/staging/westbridge/astoria/arch/arm/mach-omap2/cyashalomap_kernel.c
> 4.
> ../drivers/staging/westbridge/astoria/arch/arm/plat-omap/include/mach/westbridge/westbridge-omap3-pnand-hal/cyashalomap_kernel.h
> 5. ../drivers/staging/westbridge/astoria/device/cyasdevice.c

What is this?  We know what has been added and modified by virtue of the
patch itself.  Please use 'git format-patch' to create a patch that
includes the diffstat in it automatically, if you want to show that
(which you should.)

> Signed-off by: Sutharsan Ramamoorthy <srmt@cypress.com>

This differs from your "From:" line in your email.  If you want to
properly attribute the patch's author, please read
Documentation/SubmittingPatches to do that.

Care to try it again?

thanks,

greg k-h

Re: [PATCH] adding gpmc configuration functions, west bridge related

[Greg KH]

On Wed, Jan 12, 2011 at 12:56:44PM -0800, Sutharsan Ramamoorthy wrote:
> This patch implements gpmc configuration functions.

<snip>

Oh, and you also sent your email in html format, which caused the
mailing lists to reject it.  Please fix this as well.

thanks,

greg k-h

[PATCH] adding gpmc configuration functions, west bridge related

[Sutharsan Ramamoorthy]

This patch implements gpmc configuration functions needed by westbridge
device controller driver in staging tree. These functions currently 
implemented in staging tree. This patch is part of the effort to bring 
westbridge device controller driver out of staging tree.

Signed-off by: Sutharsan Ramamoorthy <sutharsan.ramamoorthy@yahoo.com>

---

diff -uprN -X linux-2.6.37_vanilla/Documentation/dontdiff linux-2.6.37_vanilla/arch/arm/mach-omap2/board-zoom-peripherals.c linux-2.6.37-gpmc/arch/arm/mach-omap2/board-zoom-peripherals.c
--- linux-2.6.37_vanilla/arch/arm/mach-omap2/board-zoom-peripherals.c	2010-11-29 20:42:04.000000000 -0800
+++ linux-2.6.37-gpmc/arch/arm/mach-omap2/board-zoom-peripherals.c	2011-01-11 13:33:20.750681000 -0800
@@ -19,6 +19,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/wl12xx.h>
 #include <linux/mmc/host.h>
+#include <linux/usb/cywb.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -348,6 +349,9 @@ void __init zoom_peripherals_init(void)
 	omap_i2c_init();
 	platform_device_register(&omap_vwlan_device);
 	usb_musb_init(&musb_board_data);
+#ifdef CONFIG_WESTBRIDGE_ASTORIA
+	usb_cywb_init();
+#endif
 	enable_board_wakeup_source();
 	omap_serial_init();
 }
diff -uprN -X linux-2.6.37_vanilla/Documentation/dontdiff linux-2.6.37_vanilla/arch/arm/mach-omap2/Makefile linux-2.6.37-gpmc/arch/arm/mach-omap2/Makefile
--- linux-2.6.37_vanilla/arch/arm/mach-omap2/Makefile	2010-11-29 20:42:04.000000000 -0800
+++ linux-2.6.37-gpmc/arch/arm/mach-omap2/Makefile	2010-12-28 15:24:28.218691000 -0800
@@ -182,6 +182,7 @@ obj-y					+= $(usbfs-m) $(usbfs-y)
 obj-y					+= usb-musb.o
 obj-$(CONFIG_MACH_OMAP2_TUSB6010)	+= usb-tusb6010.o
 obj-y					+= usb-ehci.o
+obj-$(CONFIG_WESTBRIDGE_ASTORIA)        += usb-cywb-pnand.o
 
 onenand-$(CONFIG_MTD_ONENAND_OMAP2)	:= gpmc-onenand.o
 obj-y					+= $(onenand-m) $(onenand-y)
diff -uprN -X linux-2.6.37_vanilla/Documentation/dontdiff linux-2.6.37_vanilla/arch/arm/mach-omap2/usb-cywb-pnand.c linux-2.6.37-gpmc/arch/arm/mach-omap2/usb-cywb-pnand.c
--- linux-2.6.37_vanilla/arch/arm/mach-omap2/usb-cywb-pnand.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-2.6.37-gpmc/arch/arm/mach-omap2/usb-cywb-pnand.c	2011-01-12 12:37:23.154716913 -0800
@@ -0,0 +1,171 @@
+/*
+ * linux /arch/arm/mach-omap2/usb-cywb-pnand.c
+ *
+ * Copyright (C) 2010  Cypress Semiconductor
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/usb/cywb.h>
+#include <plat/gpmc.h>
+
+/*
+ * chip select number on GPMC ( 0..7 )
+ */
+#define AST_GPMC_CS 4
+
+/*
+ * for use by gpmc_set_timings api, measured in ns, not clocks
+ */
+#define WB_GPMC_BUSCYC_T    (7 * 6)
+#define WB_GPMC_CS_T_O_N    (0)
+#define WB_GPMC_ADV_T_O_N   (0)
+#define WB_GPMC_OE_T_O_N    (0)
+#define WB_GPMC_OE_T_O_F_F  (5 * 6)
+#define WB_GPMC_WE_T_O_N    (1 * 6)
+#define WB_GPMC_WE_T_O_F_F  (5 * 6)
+#define WB_GPMC_RDS_ADJ     (2 * 6)
+#define WB_GPMC_RD_T_A_C_C  (WB_GPMC_OE_T_O_F_F + WB_GPMC_RDS_ADJ)
+#define WB_GPMC_WR_T_A_C_C  (WB_GPMC_BUSCYC_T)
+
+#define AS_CS_MASK	(0X7 << 8)
+#define AS_CS_BADDR	 0x02
+#define CSVALID_B (1 << 6)
+
+#define BLKSZ_4K 0x1000
+
+/*
+ * switch GPMC DATA bus mode
+ */
+void cywb_gpmc_enable_16bit_bus(bool dbus16_enabled)
+{
+	u32 tmp32;
+
+	/*
+	 * disable gpmc CS4 operation 1st
+	 */
+	tmp32 = gpmc_cs_read_reg(AST_GPMC_CS,
+				GPMC_CS_CONFIG7) & ~GPMC_CONFIG7_CSVALID;
+	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7, tmp32);
+
+	/*
+	 * GPMC NAND data bus can be 8 or 16 bit wide
+	 */
+	if (dbus16_enabled) {
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
+				(GPMC_CONFIG1_DEVICETYPE(2) |
+				GPMC_CONFIG1_WAIT_PIN_SEL(2) |
+				GPMC_CONFIG1_DEVICESIZE_16));
+	} else {
+		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
+				(GPMC_CONFIG1_DEVICETYPE(2) |
+				GPMC_CONFIG1_WAIT_PIN_SEL(2)));
+	}
+
+	/*
+	 * re-enable astoria CS operation on GPMC
+	 */
+	 gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
+			(tmp32 | GPMC_CONFIG7_CSVALID));
+}
+
+int cywb_pnand_platform_retime()
+{
+	u32 tmp32;
+	struct gpmc_timings timings;
+	int retval = 0;
+
+
+	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
+					(GPMC_CONFIG1_DEVICETYPE(2) |
+					GPMC_CONFIG1_WAIT_PIN_SEL(2)));
+
+	memset(&timings, 0, sizeof(timings));
+
+	/* cs timing */
+	timings.cs_on = WB_GPMC_CS_T_O_N;
+	timings.cs_wr_off = WB_GPMC_BUSCYC_T;
+	timings.cs_rd_off = WB_GPMC_BUSCYC_T;
+
+	/* adv timing */
+	timings.adv_on = WB_GPMC_ADV_T_O_N;
+	timings.adv_rd_off = WB_GPMC_BUSCYC_T;
+	timings.adv_wr_off = WB_GPMC_BUSCYC_T;
+
+	/* oe timing */
+	timings.oe_on = WB_GPMC_OE_T_O_N;
+	timings.oe_off = WB_GPMC_OE_T_O_F_F;
+	timings.access = WB_GPMC_RD_T_A_C_C;
+	timings.rd_cycle = WB_GPMC_BUSCYC_T;
+
+	/* we timing */
+	timings.we_on = WB_GPMC_WE_T_O_N;
+	timings.we_off = WB_GPMC_WE_T_O_F_F;
+	timings.wr_access = WB_GPMC_WR_T_A_C_C;
+	timings.wr_cycle = WB_GPMC_BUSCYC_T;
+
+	timings.page_burst_access = WB_GPMC_BUSCYC_T;
+	timings.wr_data_mux_bus = WB_GPMC_BUSCYC_T;
+	gpmc_cs_set_timings(AST_GPMC_CS, &timings);
+
+	/*
+	 * DISABLE cs4, NOTE GPMC REG7 is already configured
+	 * at this point by gpmc_cs_request
+	 */
+	tmp32 = gpmc_cs_read_reg(AST_GPMC_CS, GPMC_CS_CONFIG7) &
+					~GPMC_CONFIG7_CSVALID;
+	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7, tmp32);
+
+	/*
+	 * PROGRAM chip select Region, (see OMAP3430 TRM PAGE 1088)
+	 */
+	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
+				(AS_CS_MASK | AS_CS_BADDR));
+
+	/*
+	 * by default configure GPMC into 8 bit mode
+	 * (to match astoria default mode)
+	 */
+	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
+				(GPMC_CONFIG1_DEVICETYPE(2) |
+				GPMC_CONFIG1_WAIT_PIN_SEL(2)));
+
+	/*
+	 * ENABLE astoria cs operation on GPMC
+	 */
+	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
+					(tmp32 | GPMC_CONFIG7_CSVALID));
+
+	return retval;
+
+}
+
+static struct cywb_platform_data cywb_plat = {
+	.retime			= cywb_pnand_platform_retime,
+	.config_bus_width	= cywb_gpmc_enable_16bit_bus,
+};
+
+static struct platform_device cywb_device = {
+	.name		= "west_bridge_dev",
+	.id		= -1,
+	.dev = {
+		.platform_data		= &cywb_plat,
+	}
+};
+
+#ifdef CONFIG_WESTBRIDGE_ASTORIA
+void __init usb_cywb_init()
+{
+	if (platform_device_register(&cywb_device) < 0)
+		dev_err(&cywb_device.dev, "Unable to register cywb-astoria device\n");
+}
+#else
+void __init usb_cywb_init()
+{
+}
+#endif /* CONFIG_WESTBRIDGE_ASTORIA */
diff -uprN -X linux-2.6.37_vanilla/Documentation/dontdiff linux-2.6.37_vanilla/drivers/staging/westbridge/astoria/arch/arm/mach-omap2/cyashalomap_kernel.c linux-2.6.37-gpmc/drivers/staging/westbridge/astoria/arch/arm/mach-omap2/cyashalomap_kernel.c
--- linux-2.6.37_vanilla/drivers/staging/westbridge/astoria/arch/arm/mach-omap2/cyashalomap_kernel.c	2010-11-29 20:42:04.000000000 -0800
+++ linux-2.6.37-gpmc/drivers/staging/westbridge/astoria/arch/arm/mach-omap2/cyashalomap_kernel.c	2011-01-11 17:57:48.766357001 -0800
@@ -298,60 +298,17 @@ static u16 omap_cfg_reg_L(u32 pad_func_i
 
 #define BLKSZ_4K 0x1000
 
-/*
- * switch GPMC DATA bus mode
- */
-void cy_as_hal_gpmc_enable_16bit_bus(bool dbus16_enabled)
-{
-	uint32_t tmp32;
-
-	/*
-	 * disable gpmc CS4 operation 1st
-	 */
-	tmp32 = gpmc_cs_read_reg(AST_GPMC_CS,
-				GPMC_CS_CONFIG7) & ~GPMC_CONFIG7_CSVALID;
-	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7, tmp32);
-
-	/*
-	 * GPMC NAND data bus can be 8 or 16 bit wide
-	 */
-	if (dbus16_enabled) {
-		DBGPRN("enabling 16 bit bus\n");
-		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
-				(GPMC_CONFIG1_DEVICETYPE(2) |
-				GPMC_CONFIG1_WAIT_PIN_SEL(2) |
-				GPMC_CONFIG1_DEVICESIZE_16)
-				);
-	} else {
-		DBGPRN(KERN_INFO "enabling 8 bit bus\n");
-		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
-				(GPMC_CONFIG1_DEVICETYPE(2) |
-				GPMC_CONFIG1_WAIT_PIN_SEL(2))
-				);
-	}
-
-	/*
-	 * re-enable astoria CS operation on GPMC
-	 */
-	 gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
-			(tmp32 | GPMC_CONFIG7_CSVALID));
-
-	/*
-	 *remember the state
-	 */
-	pnand_16bit = dbus16_enabled;
-}
-
-static int cy_as_hal_gpmc_init(void)
+static int cy_as_hal_gpmc_init(struct cywb_platform_data *cywb_pd)
 {
 	u32 tmp32;
 	int err;
 	struct gpmc_timings	timings;
+
 	/*
 	 * get GPMC i/o registers base(already been i/o mapped
 	 * in kernel, no need for separate i/o remap)
 	 */
-	gpmc_base = phys_to_virt(OMAP34XX_GPMC_BASE);
+	gpmc_base = (u32)ioremap_nocache(OMAP34XX_GPMC_BASE, BLKSZ_4K);
 	DBGPRN(KERN_INFO "kernel has gpmc_base=%x , val@ the base=%x",
 		gpmc_base, __raw_readl(gpmc_base)
 	);
@@ -404,68 +361,7 @@ static int cy_as_hal_gpmc_init(void)
 	cy_as_hal_print_message(KERN_INFO "ioremap(%x) returned vma=%x\n",
 							csa_phy, gpmc_data_vma);
 
-	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
-						(GPMC_CONFIG1_DEVICETYPE(2) |
-						GPMC_CONFIG1_WAIT_PIN_SEL(2)));
-
-	memset(&timings, 0, sizeof(timings));
-
-	/* cs timing */
-	timings.cs_on = WB_GPMC_CS_t_o_n;
-	timings.cs_wr_off = WB_GPMC_BUSCYC_t;
-	timings.cs_rd_off = WB_GPMC_BUSCYC_t;
-
-	/* adv timing */
-	timings.adv_on = WB_GPMC_ADV_t_o_n;
-	timings.adv_rd_off = WB_GPMC_BUSCYC_t;
-	timings.adv_wr_off = WB_GPMC_BUSCYC_t;
-
-	/* oe timing */
-	timings.oe_on = WB_GPMC_OE_t_o_n;
-	timings.oe_off = WB_GPMC_OE_t_o_f_f;
-	timings.access = WB_GPMC_RD_t_a_c_c;
-	timings.rd_cycle = WB_GPMC_BUSCYC_t;
-
-	/* we timing */
-	timings.we_on = WB_GPMC_WE_t_o_n;
-	timings.we_off = WB_GPMC_WE_t_o_f_f;
-	timings.wr_access = WB_GPMC_WR_t_a_c_c;
-	timings.wr_cycle = WB_GPMC_BUSCYC_t;
-
-	timings.page_burst_access = WB_GPMC_BUSCYC_t;
-	timings.wr_data_mux_bus = WB_GPMC_BUSCYC_t;
-	gpmc_cs_set_timings(AST_GPMC_CS, &timings);
-
-	cy_as_hal_print_omap_regs("GPMC_CONFIG", 1,
-			GPMC_VMA(GPMC_CFG_REG(1, AST_GPMC_CS)), 7);
-
-	/*
-	 * DISABLE cs4, NOTE GPMC REG7 is already configured
-	 * at this point by gpmc_cs_request
-	 */
-	tmp32 = gpmc_cs_read_reg(AST_GPMC_CS, GPMC_CS_CONFIG7) &
-						~GPMC_CONFIG7_CSVALID;
-	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7, tmp32);
-
-	/*
-	 * PROGRAM chip select Region, (see OMAP3430 TRM PAGE 1088)
-	 */
-	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
-					(AS_CS_MASK | AS_CS_BADDR));
-
-	/*
-	 * by default configure GPMC into 8 bit mode
-	 * (to match astoria default mode)
-	 */
-	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
-					(GPMC_CONFIG1_DEVICETYPE(2) |
-					GPMC_CONFIG1_WAIT_PIN_SEL(2)));
-
-	/*
-	 * ENABLE astoria cs operation on GPMC
-	 */
-	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
-					(tmp32 | GPMC_CONFIG7_CSVALID));
+	cywb_pd->retime();
 
 	/*
 	 * No method currently exists to write this register through GPMC APIs
@@ -749,7 +645,7 @@ EXPORT_SYMBOL(cy_as_hal_config_c_s_mux);
 /*
  * inits all omap h/w
  */
-uint32_t cy_as_hal_processor_hw_init(void)
+uint32_t cy_as_hal_processor_hw_init(struct cywb_platform_data *cywb_pd)
 {
 	int i, err;
 
@@ -789,7 +685,7 @@ uint32_t cy_as_hal_processor_hw_init(voi
 	 */
 	cy_as_hal_init_user_pads(user_pad_cfg);
 
-	err = cy_as_hal_gpmc_init();
+	err = cy_as_hal_gpmc_init(cywb_pd);
 	if (err < 0)
 		cy_as_hal_print_message(KERN_INFO"gpmc init failed:%d", err);
 
@@ -2285,7 +2181,9 @@ cy_bool cy_as_hal_sync_device_clocks(cy_
  * init OMAP h/w resources
  */
 int start_o_m_a_p_kernel(const char *pgm,
-				cy_as_hal_device_tag *tag, cy_bool debug)
+				cy_as_hal_device_tag *tag,
+				struct cywb_platform_data *cywb_pd,
+				cy_bool debug)
 {
 	cy_as_omap_dev_kernel *dev_p;
 	int i;
@@ -2333,7 +2231,7 @@ int start_o_m_a_p_kernel(const char *pgm
 	/*
 	 * initialize OMAP hardware and StartOMAPKernelall gpio pins
 	 */
-	dev_p->m_addr_base = (void *)cy_as_hal_processor_hw_init();
+	dev_p->m_addr_base = (void *)cy_as_hal_processor_hw_init(cywb_pd);
 
 	/*
 	 * Now perform a hard reset of the device to have
@@ -2361,7 +2259,6 @@ int start_o_m_a_p_kernel(const char *pgm
 	pncfg_reg = ast_p_nand_casdo_read(CY_AS_MEM_PNAND_CFG);
 
 #ifdef PNAND_16BIT_MODE
-
 	/*
 	 * switch to 16 bit mode, force NON-LNA LBD mode, 3 RA addr bytes
 	 */
@@ -2370,8 +2267,12 @@ int start_o_m_a_p_kernel(const char *pgm
 	/*
 	 * now in order to continue to talk to astoria
 	 * sw OMAP GPMC into 16 bit mode as well
+	 *
+	 * remember bus width state
+	 * pnand_16bit = cy_true  - bus width is 16-bit
 	 */
-	cy_as_hal_gpmc_enable_16bit_bus(cy_true);
+	pnand_16bit = cy_true;
+	cywb_pd->config_bus_width(pnand_16bit);
 #else
    /* Astoria and GPMC are already in 8 bit mode, jsut initialize PNAND_CFG */
 	ast_p_nand_casdi_write(CY_AS_MEM_PNAND_CFG, 0x0000);
diff -uprN -X linux-2.6.37_vanilla/Documentation/dontdiff linux-2.6.37_vanilla/drivers/staging/westbridge/astoria/arch/arm/plat-omap/include/mach/westbridge/westbridge-omap3-pnand-hal/cyashalomap_kernel.h linux-2.6.37-gpmc/drivers/staging/westbridge/astoria/arch/arm/plat-omap/include/mach/westbridge/westbridge-omap3-pnand-hal/cyashalomap_kernel.h
--- linux-2.6.37_vanilla/drivers/staging/westbridge/astoria/arch/arm/plat-omap/include/mach/westbridge/westbridge-omap3-pnand-hal/cyashalomap_kernel.h	2010-11-29 20:42:04.000000000 -0800
+++ linux-2.6.37-gpmc/drivers/staging/westbridge/astoria/arch/arm/plat-omap/include/mach/westbridge/westbridge-omap3-pnand-hal/cyashalomap_kernel.h	2011-01-11 17:58:50.862357870 -0800
@@ -32,6 +32,7 @@
 #include <linux/module.h>
 #include <linux/wait.h>
 #include <linux/string.h>
+#include <linux/usb/cywb.h>
 /* include does not seem to work
  * moving for patch submission
 #include <mach/gpmc.h>
@@ -307,7 +308,9 @@ void cyashal_prn_buf(void  *buf, uint16_
  * but are required to be called for this HAL.
  */
 int start_o_m_a_p_kernel(const char *pgm,
-	cy_as_hal_device_tag *tag, cy_bool debug);
+	cy_as_hal_device_tag *tag,
+	struct cywb_platform_data *cywb_pd,
+	cy_bool debug);
 int stop_o_m_a_p_kernel(const char *pgm, cy_as_hal_device_tag tag);
 int omap_start_intr(cy_as_hal_device_tag tag);
 void cy_as_hal_set_ep_dma_mode(uint8_t ep, bool sg_xfer_enabled);
diff -uprN -X linux-2.6.37_vanilla/Documentation/dontdiff linux-2.6.37_vanilla/drivers/staging/westbridge/astoria/device/cyasdevice.c linux-2.6.37-gpmc/drivers/staging/westbridge/astoria/device/cyasdevice.c
--- linux-2.6.37_vanilla/drivers/staging/westbridge/astoria/device/cyasdevice.c	2010-11-29 20:42:04.000000000 -0800
+++ linux-2.6.37-gpmc/drivers/staging/westbridge/astoria/device/cyasdevice.c	2011-01-12 11:57:02.671217929 -0800
@@ -28,6 +28,7 @@
 #include <linux/firmware.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
+#include <linux/usb/cywb.h>
 
 /* moved for staging location
  * update/patch submission
@@ -57,6 +58,7 @@ static cyasdevice *cy_as_device_controll
 int cy_as_device_init_done;
 const char *dev_handle_name = "cy_astoria_dev_handle";
 
+static int cyasdevice_initialize(void);
 #ifdef CONFIG_MACH_OMAP3_WESTBRIDGE_AST_PNAND_HAL
 extern void cy_as_hal_config_c_s_mux(void);
 #endif
@@ -172,6 +174,10 @@ static struct platform_device *westbridg
 static int __devinit wb_probe(struct platform_device *devptr)
 {
 	cy_as_hal_print_message("%s called\n", __func__);
+	westbridge_pd = devptr;
+	if (cyasdevice_initialize() != 0)
+		return -ENODEV;
+
 	return 0;
 }
 
@@ -229,8 +235,9 @@ static int cyasdevice_initialize(void)
  /* start OMAP HAL init instsnce */
 
 	if (!start_o_m_a_p_kernel(dev_handle_name,
-		&(cy_as_dev->hal_tag), cy_false)) {
-
+		&(cy_as_dev->hal_tag),
+		westbridge_pd ? westbridge_pd->dev.platform_data : NULL,
+		cy_false)) {
 		cy_as_hal_print_message(
 			"<1>_cy_as_device: start OMAP34xx HAL failed\n");
 		goto done;
@@ -267,16 +274,6 @@ static int cyasdevice_initialize(void)
 		goto done;
 	}
 
-	ret = platform_driver_register(&west_bridge_driver);
-	if (unlikely(ret < 0))
-		return ret;
-	westbridge_pd = platform_device_register_simple(
-		"west_bridge_dev", -1, NULL, 0);
-
-	if (IS_ERR(westbridge_pd)) {
-		platform_driver_unregister(&west_bridge_driver);
-		return PTR_ERR(westbridge_pd);
-	}
 	/* Load the firmware */
 	ret = request_firmware(&fw_entry,
 		"west bridge fw", &westbridge_pd->dev);
@@ -384,17 +381,12 @@ cy_as_hal_device_tag cyasdevice_gethalta
 }
 EXPORT_SYMBOL(cyasdevice_gethaltag);
 
-
 /*init Westbridge device driver **/
 static int __init cyasdevice_init(void)
 {
-	if (cyasdevice_initialize() != 0)
-		return ENODEV;
-
-	return 0;
+	return platform_driver_register(&west_bridge_driver);
 }
 
-
 static void __exit cyasdevice_cleanup(void)
 {
 
diff -uprN -X linux-2.6.37_vanilla/Documentation/dontdiff linux-2.6.37_vanilla/include/linux/usb/cywb.h linux-2.6.37-gpmc/include/linux/usb/cywb.h
--- linux-2.6.37_vanilla/include/linux/usb/cywb.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-2.6.37-gpmc/include/linux/usb/cywb.h	2011-01-12 12:35:40.054775557 -0800
@@ -0,0 +1,21 @@
+/*
+ * data structure declaration for passing gpmc configuration
+ * functions to westbridge device controller driver.
+ * usb-cywb-pnand.c defines the configuration functions
+ */
+
+#ifndef __LINUX_USB_CYWB_H
+#define __LINUX_USB_CYWB_H
+
+
+struct cywb_platform_data {
+	/* PNAND retime function */
+	int		(*retime)(void);
+
+	/* PNAND bus width configuration */
+	void		(*config_bus_width)(bool dbus16_enabled);
+};
+
+extern void usb_cywb_init(void);
+
+#endif /* __LINUX_USB_CYWB_H */


      

Re: [PATCH] adding gpmc configuration functions, west bridge related

[Greg KH]

On Thu, Jan 13, 2011 at 03:23:14PM -0800, Sutharsan Ramamoorthy wrote:
> This patch implements gpmc configuration functions needed by westbridge
> device controller driver in staging tree. These functions currently 
> implemented in staging tree. This patch is part of the effort to bring 
> westbridge device controller driver out of staging tree.
> 
> Signed-off by: Sutharsan Ramamoorthy <sutharsan.ramamoorthy@yahoo.com>

Close, but not quite.

Why remove your cypress.com email address here?  That's who really is
"signing off" on this patch, right?

Also, please note my previous comments about "lots more needs to be done
to the driver before this can even start to move out of the staging
tree".  Moving these functions should be one of the _last_ things that
happens, not the first.

Please work on cleaning up the code in the drivers/staging/westbridge/
directory first.  When that is all done, _then_ we can start moving it
out.

Ok?

thanks,

greg k-h

Re: [PATCH] adding gpmc configuration functions, west bridge related

[Tony Lindgren]

* Sutharsan Ramamoorthy <sutharsan.ramamoorthy@yahoo.com> [110113 15:22]:
> --- linux-2.6.37_vanilla/arch/arm/mach-omap2/usb-cywb-pnand.c	1969-12-31 16:00:00.000000000 -0800
> +++ linux-2.6.37-gpmc/arch/arm/mach-omap2/usb-cywb-pnand.c	2011-01-12 12:37:23.154716913 -0800
...

> +/*
> + * switch GPMC DATA bus mode
> + */
> +void cywb_gpmc_enable_16bit_bus(bool dbus16_enabled)
> +{
> +	u32 tmp32;
> +
> +	/*
> +	 * disable gpmc CS4 operation 1st
> +	 */
> +	tmp32 = gpmc_cs_read_reg(AST_GPMC_CS,
> +				GPMC_CS_CONFIG7) & ~GPMC_CONFIG7_CSVALID;
> +	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7, tmp32);
> +
> +	/*
> +	 * GPMC NAND data bus can be 8 or 16 bit wide
> +	 */
> +	if (dbus16_enabled) {
> +		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
> +				(GPMC_CONFIG1_DEVICETYPE(2) |
> +				GPMC_CONFIG1_WAIT_PIN_SEL(2) |
> +				GPMC_CONFIG1_DEVICESIZE_16));
> +	} else {
> +		gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
> +				(GPMC_CONFIG1_DEVICETYPE(2) |
> +				GPMC_CONFIG1_WAIT_PIN_SEL(2)));
> +	}
> +
> +	/*
> +	 * re-enable astoria CS operation on GPMC
> +	 */
> +	 gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
> +			(tmp32 | GPMC_CONFIG7_CSVALID));
> +}

This should be static, right?


> +int cywb_pnand_platform_retime()
> +{
> +	u32 tmp32;
> +	struct gpmc_timings timings;
> +	int retval = 0;
> +
> +
> +	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
> +					(GPMC_CONFIG1_DEVICETYPE(2) |
> +					GPMC_CONFIG1_WAIT_PIN_SEL(2)));
> +
> +	memset(&timings, 0, sizeof(timings));
> +
> +	/* cs timing */
> +	timings.cs_on = WB_GPMC_CS_T_O_N;
> +	timings.cs_wr_off = WB_GPMC_BUSCYC_T;
> +	timings.cs_rd_off = WB_GPMC_BUSCYC_T;
> +
> +	/* adv timing */
> +	timings.adv_on = WB_GPMC_ADV_T_O_N;
> +	timings.adv_rd_off = WB_GPMC_BUSCYC_T;
> +	timings.adv_wr_off = WB_GPMC_BUSCYC_T;
> +
> +	/* oe timing */
> +	timings.oe_on = WB_GPMC_OE_T_O_N;
> +	timings.oe_off = WB_GPMC_OE_T_O_F_F;
> +	timings.access = WB_GPMC_RD_T_A_C_C;
> +	timings.rd_cycle = WB_GPMC_BUSCYC_T;
> +
> +	/* we timing */
> +	timings.we_on = WB_GPMC_WE_T_O_N;
> +	timings.we_off = WB_GPMC_WE_T_O_F_F;
> +	timings.wr_access = WB_GPMC_WR_T_A_C_C;
> +	timings.wr_cycle = WB_GPMC_BUSCYC_T;
> +
> +	timings.page_burst_access = WB_GPMC_BUSCYC_T;
> +	timings.wr_data_mux_bus = WB_GPMC_BUSCYC_T;
> +	gpmc_cs_set_timings(AST_GPMC_CS, &timings);
> +
> +	/*
> +	 * DISABLE cs4, NOTE GPMC REG7 is already configured
> +	 * at this point by gpmc_cs_request
> +	 */
> +	tmp32 = gpmc_cs_read_reg(AST_GPMC_CS, GPMC_CS_CONFIG7) &
> +					~GPMC_CONFIG7_CSVALID;
> +	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7, tmp32);
> +
> +	/*
> +	 * PROGRAM chip select Region, (see OMAP3430 TRM PAGE 1088)
> +	 */
> +	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
> +				(AS_CS_MASK | AS_CS_BADDR));
> +
> +	/*
> +	 * by default configure GPMC into 8 bit mode
> +	 * (to match astoria default mode)
> +	 */
> +	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
> +				(GPMC_CONFIG1_DEVICETYPE(2) |
> +				GPMC_CONFIG1_WAIT_PIN_SEL(2)));
> +
> +	/*
> +	 * ENABLE astoria cs operation on GPMC
> +	 */
> +	gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
> +					(tmp32 | GPMC_CONFIG7_CSVALID));
> +
> +	return retval;
> +
> +}
> +
> +static struct cywb_platform_data cywb_plat = {
> +	.retime			= cywb_pnand_platform_retime,
> +	.config_bus_width	= cywb_gpmc_enable_16bit_bus,
> +};
> +
> +static struct platform_device cywb_device = {
> +	.name		= "west_bridge_dev",
> +	.id		= -1,
> +	.dev = {
> +		.platform_data		= &cywb_plat,
> +	}
> +};
> +
> +#ifdef CONFIG_WESTBRIDGE_ASTORIA
> +void __init usb_cywb_init()
> +{
> +	if (platform_device_register(&cywb_device) < 0)
> +		dev_err(&cywb_device.dev, "Unable to register cywb-astoria device\n");
> +}
> +#else
> +void __init usb_cywb_init()
> +{
> +}
> +#endif /* CONFIG_WESTBRIDGE_ASTORIA */

Can you also move gpmc_cs_request to this file too?

Regards,

Tony