From: Andi Kleen <andi@firstfloor.org>
To: Stephane Eranian <eranian@google.com>
Cc: Lin Ming <ming.m.lin@intel.com>,
Peter Zijlstra <a.p.zijlstra@chello.nl>,
Ingo Molnar <mingo@elte.hu>, Andi Kleen <andi@firstfloor.org>,
lkml <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/7] perf-events: Add support for supplementary event registers v4
Date: Thu, 13 Jan 2011 21:41:55 +0100 [thread overview]
Message-ID: <20110113204155.GQ25713@one.firstfloor.org> (raw)
In-Reply-To: <AANLkTik9adcY_pH52c_Y0iRjitDKZOu5zyPusfjycuiH@mail.gmail.com>
On Thu, Jan 13, 2011 at 06:31:03PM +0100, Stephane Eranian wrote:
> Hi,
>
> I'd like to suggest that the OFFCORE_RESPONSE extra MSR encoding
> be put into a dedicated field in the perf_event_attr instead of in the upper
> 32-bits of attr->config.
That's what the first revision of the patch did.
I can change it back to that.
Small drawback was that it needs more changes to the user tool,
but the patch was not very big.
>
> There may not be enough space to encode for future processors.
>
> In fact, given that the Sandy Bridge PMU spec is now available, we
> have a first example of this (see Vol3b figure 30.29). OFFCORE_RESPONSE
> needs 38 bits. So, instead of having NHM/WSM use attr->config and SNB
That makes sense.
> use another field, I think it would make sense to have that in a new u64 field
> for all processors. Despite the fact that OFFCORE_RESPONSE remains
> a model-specific feature, I think it would help user tools and libraries if we
> were to use a dedicated field.
-Andi
prev parent reply other threads:[~2011-01-13 20:42 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-12-27 15:36 [PATCH 2/7] perf-events: Add support for supplementary event registers v4 Lin Ming
2011-01-13 17:31 ` Stephane Eranian
2011-01-13 17:41 ` Peter Zijlstra
2011-01-13 20:41 ` Andi Kleen [this message]
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