Re: [tip:perfcounters/core] perf_counter: x86: Fix call-chain support to use NMI-safe methods

Mathieu Desnoyers
2009-06-15T21:12:24Z

* Ingo Molnar (mingo@elte.hu) wrote:
>
> * H. Peter Anvin <hpa@zytor.com> wrote:
>
> > Mathieu Desnoyers wrote:
> > >>>
> > >> Writing control registers is serializing, so it's a lot more expensive
> > >> than writing a normal register; my *guess* is that it will be on the
> > >> order of 100-200 cycles.
> > >>
> > >> That is not based on any actual information.
> > >>
> > >
> > > Then how about just writing to the cr2 register *if* it has changed
> > > while the NMI handler was running ?
> > >
> > > if (unlikely(read_cr2() != saved_cr2)))
> > > write_cr2(saved_cr2)
> > >
> > > Mathieu
> > >
> >
> > That works fine, obviously, and although it's probably overkill
> > it's also a trivially cheap optimization.
>
> Writing cr2 costs 84 cycles so it's not overkill at all - it's a
> nice optimization!
>
> Btw., we dont have to re-read it - we actually _know_ when we got a
> fault (the fault handler gives us back an error code).
>

Just for the sake of making NMI handlers less tricky, supporting page
faults caused by faulting kernel instructions (rather than only
supporting explicit faulting from get_user_pages_inatomic) would be
rather nice design-wise if it only costs 2-3 cycles.

And I would not want to touch the page fault handler itself to write the
saved cr2 value before the handler exits, because this would add a
branch on a very hot path.

Mathieu

> So we can do this common optimization and avoid the cr2 write
> usually. We only need the cr2 read.
>
> Hm, tempting ...
>
> Ingo

--
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F BA06 3F25 A8FE 3BAE 9A68