From: "Rafael J. Wysocki" <rjw@sisk.pl>
To: Alan Stern <stern@rowland.harvard.edu>
Cc: Mike Frysinger <vapier@gentoo.org>,
uclinux-dist-devel@blackfin.uclinux.org,
linux-pm@lists.linux-foundation.org,
linux-kernel@vger.kernel.org
Subject: Re: [linux-pm] [uclinux-dist-devel] freezer: should barriers be smp?
Date: Thu, 14 Apr 2011 00:34:41 +0200 [thread overview]
Message-ID: <201104140034.41727.rjw@sisk.pl> (raw)
In-Reply-To: <Pine.LNX.4.44L0.1104131805090.2005-100000@iolanthe.rowland.org>
On Thursday, April 14, 2011, Alan Stern wrote:
> On Wed, 13 Apr 2011, Rafael J. Wysocki wrote:
>
> > The above means that smp_*mb() are defined as *mb() if CONFIG_SMP is set,
> > which basically means that *mb() are more restrictive than the corresponding
> > smp_*mb(). More precisely, they also cover the cases in which the CPU
> > reorders instructions on uniprocessor, which we definitely want to cover.
> >
> > IOW, your patch would break things on uniprocessor where the CPU reorders
> > instructions.
>
> How could anything break on a UP system? CPUs don't reorder
> instructions that drastically. For example, no CPU will ever violate
> this assertion:
>
> x = 0;
> y = x;
> x = 1;
> assert(y == 0);
>
> even if it does reorder the second and third statements internally.
> This is guaranteed by the C language specification.
Well, you conveniently removed the patch from your reply. :-)
For example, there's no reason why the CPU cannot reorder things so that
the "if (frozen(p))" is (speculatively) done before the "if (!freezing(p))"
if there's only a compiler barrier between them.
> > > Documentation/memory-barriers.txt:
> > > SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
> > > systems because it is assumed that a CPU will appear to be self-consistent,
> > > and will order overlapping accesses correctly with respect to itself.
> >
> > Exactly, which is not guaranteed in general (e.g. on Alpha). That is, some
> > CPUs can reorder instructions in such a way that a compiler barrier is not
> > sufficient to prevent breakage.
>
> I don't think this is right. You _can_ assume that Alphas appear to be
> self-consistent. If they didn't, you wouldn't be able to use them at
> all.
I'm quite convinced that the statement "some CPUs can reorder instructions in
such a way that a compiler barrier is not sufficient to prevent breakage" is
correct.
Thanks,
Rafael
next prev parent reply other threads:[~2011-04-13 22:34 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-13 6:14 freezer: should barriers be smp ? Mike Frysinger
2011-04-13 20:58 ` Rafael J. Wysocki
2011-04-13 21:02 ` Mike Frysinger
2011-04-13 21:05 ` Pavel Machek
2011-04-13 21:11 ` [uclinux-dist-devel] " Mike Frysinger
2011-04-13 21:53 ` Rafael J. Wysocki
2011-04-13 22:11 ` [linux-pm] " Alan Stern
2011-04-13 22:34 ` Rafael J. Wysocki [this message]
2011-04-14 14:55 ` [linux-pm] [uclinux-dist-devel] freezer: should barriers be smp? Alan Stern
2011-04-14 22:34 ` Rafael J. Wysocki
2011-04-15 14:32 ` Alan Stern
2011-04-13 22:22 ` [uclinux-dist-devel] freezer: should barriers be smp ? Mike Frysinger
2011-04-13 22:49 ` Rafael J. Wysocki
2011-04-13 22:53 ` Rafael J. Wysocki
2011-04-13 22:57 ` Mike Frysinger
2011-04-13 23:12 ` Rafael J. Wysocki
2011-04-14 15:13 ` [linux-pm] " Alan Stern
2011-04-14 22:40 ` Rafael J. Wysocki
2011-04-13 22:04 ` [linux-pm] [uclinux-dist-devel] " Alan Stern
2011-04-15 16:29 ` Pavel Machek
2011-04-15 16:33 ` [uclinux-dist-devel] [linux-pm] " Mike Frysinger
2011-04-15 16:57 ` Pavel Machek
2011-04-15 23:11 ` Rafael J. Wysocki
2011-04-15 23:24 ` Mike Frysinger
2011-04-15 23:30 ` Rafael J. Wysocki
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