* [PATCH] mfd: fix tps6586x GPIO value setting
@ 2011-04-12 14:55 Vincent Palatin
2011-05-02 9:21 ` Samuel Ortiz
0 siblings, 1 reply; 2+ messages in thread
From: Vincent Palatin @ 2011-04-12 14:55 UTC (permalink / raw)
To: Samuel Ortiz, LKML; +Cc: Olof Johansson, Vincent Palatin
In the current code, every time we set a TPS6586x GPIO pin,
the tps6586x_gpio_set function is resetting all other GPIO pins.
We need to update the right GPIOxOUT bit of the GPIOSET2 register instead
of overriding the full value.
Tested by setting sequentially GPIO2 and GPIO3 and verifying the
pins voltage.
Change-Id: I560edde146c5425cce37432c4ee91569eea5adcf
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
---
drivers/mfd/tps6586x.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mfd/tps6586x.c b/drivers/mfd/tps6586x.c
index b600808..bba26d9 100644
--- a/drivers/mfd/tps6586x.c
+++ b/drivers/mfd/tps6586x.c
@@ -270,8 +270,8 @@ static void tps6586x_gpio_set(struct gpio_chip *chip, unsigned offset,
{
struct tps6586x *tps6586x = container_of(chip, struct tps6586x, gpio);
- __tps6586x_write(tps6586x->client, TPS6586X_GPIOSET2,
- value << offset);
+ tps6586x_update(tps6586x->dev, TPS6586X_GPIOSET2,
+ value << offset, 1 << offset);
}
static int tps6586x_gpio_output(struct gpio_chip *gc, unsigned offset,
--
1.7.3.1
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] mfd: fix tps6586x GPIO value setting
2011-04-12 14:55 [PATCH] mfd: fix tps6586x GPIO value setting Vincent Palatin
@ 2011-05-02 9:21 ` Samuel Ortiz
0 siblings, 0 replies; 2+ messages in thread
From: Samuel Ortiz @ 2011-05-02 9:21 UTC (permalink / raw)
To: Vincent Palatin; +Cc: LKML, Olof Johansson
Hi Vincent,
On Tue, Apr 12, 2011 at 10:55:58AM -0400, Vincent Palatin wrote:
> In the current code, every time we set a TPS6586x GPIO pin,
> the tps6586x_gpio_set function is resetting all other GPIO pins.
> We need to update the right GPIOxOUT bit of the GPIOSET2 register instead
> of overriding the full value.
>
> Tested by setting sequentially GPIO2 and GPIO3 and verifying the
> pins voltage.
Patch applied to my for-next branch, thanks.
Cheers,
Samuel.
--
Intel Open Source Technology Centre
http://oss.intel.com/
^ permalink raw reply [flat|nested] 2+ messages in thread
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