Re: [PATCH] cpu, AMD: Fix another bug in the new errata checking code

[Chuck Ebbert <cebbert@redhat.com>]

On Fri, 13 May 2011 09:03:59 -0400
Boris Ostrovsky <boris.ostrovsky@amd.com> wrote:

> On 05/13/2011 06:21 AM, Hans Rosenfeld wrote:
> > On Thu, May 12, 2011 at 07:59:38PM -0400, Chuck Ebbert wrote:
> > The revision guide states that family 0x10 model 6 stepping 2 has E400.
> > So I would expect that OSVW length is>= 2 and that OSVW status has bit
> > 1 set, or that OSVW length is<  2. This indicates that the workaround is
> > necessary, without any need to check the family-model-stepping ranges.
> >
> > It would also be correct if the BIOS disabled C1E and cleared the
> > corresponding OSVW status bit. Anything else would probably be a very
> > nasty BIOS bug.
> >

> > Could you send me the contents of MSRs 0xc0010140, 0xc0010141 and
> > 0xc0010055?
> 
> Knowing whether any C state above C1 is declared could be useful too.
> 
rdmsr 0xc0010140 gives 2
rdmsr 0xc0010141 gives 0
rdmsr 0xc0010055 gives 0

And ARAT is definitely set where it wasn't before these updates.

BTW we now have multiple reports of this, one system is a Compaq Presario
CQ61 with an AMD Sempron M120 processor.

I'll check on the C-states next.