From: Andi Kleen <andi@firstfloor.org>
To: Stephane Eranian <eranian@google.com>
Cc: linux-kernel@vger.kernel.org, mingo@elte.hu,
peterz@infradead.org, andi@firstfloor.org, ming.m.lin@intel.com
Subject: Re: [PATCH 1/3] perf_events: update Intel extra regs shared constraints management (v3)
Date: Mon, 23 May 2011 18:44:21 +0200 [thread overview]
Message-ID: <20110523164421.GC15299@one.firstfloor.org> (raw)
In-Reply-To: <20110523161247.GA11590@quad>
On Mon, May 23, 2011 at 06:12:47PM +0200, Stephane Eranian wrote:
>
> This patch improves the code managing the extra shared registers
> used for offcore_response events on Intel Nehalem/Westmere. The
> idea is to use static allocation instead of dynamic allocation.
> This simplifies greatly the get and put constraint routines for
> those events.
>
> The patch also renames per_core to shared_regs because the same
> data structure gets used whether or not HT is on. When HT is
> off, those events still need to coordination because they use
> a extra MSR that has to be shared within an event group.
>
> The first post of this patch had an older (bogus) version of
> the patch with bogus initialization of reg->idx.
I did a quick read -- not full check -- and it looked good to me.
I like the idea of preallocating the slots.
Acked-by: Andi Kleen <ak@linux.intel.com>
-Andi
prev parent reply other threads:[~2011-05-23 16:44 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-05-23 16:12 [PATCH 1/3] perf_events: update Intel extra regs shared constraints management (v3) Stephane Eranian
2011-05-23 16:44 ` Andi Kleen [this message]
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