From: Andi Kleen <andi@firstfloor.org>
To: Lin Ming <ming.m.lin@intel.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>,
Ingo Molnar <mingo@elte.hu>, Andi Kleen <andi@firstfloor.org>,
Stephane Eranian <eranian@google.com>,
Arnaldo Carvalho de Melo <acme@ghostprotocols.net>,
linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/4] perf, x86: Add Intel Nehalem/Westmere uncore pmu
Date: Thu, 30 Jun 2011 18:58:49 +0200 [thread overview]
Message-ID: <20110630165849.GE23059@one.firstfloor.org> (raw)
In-Reply-To: <1309421396-17438-2-git-send-email-ming.m.lin@intel.com>
On Thu, Jun 30, 2011 at 08:09:53AM +0000, Lin Ming wrote:
> +static u64 uncore_perf_event_update(struct perf_event *event)
> +{
> + struct hw_perf_event *hwc = &event->hw;
> + int shift = 64 - intel_uncore_pmu.cntval_bits;
> + u64 prev_raw_count, new_raw_count;
> + s64 delta;
> +
> + /*
> + * Careful: an NMI might modify the previous event value.
There are no NMIs without sampling, so at least the comment seems bogus.
Perhaps the code could be a bit simplified now without atomics.
> +static int uncore_pmu_event_init(struct perf_event *event)
> +{
> + struct hw_perf_event *hwc = &event->hw;
> +
> + if (!uncore_pmu_initialized)
> + return -ENOENT;
> +
> + if (event->attr.type != uncore_pmu.type)
> + return -ENOENT;
> +
> + /*
> + * Uncore PMU does measure at all privilege level all the time.
> + * So it doesn't make sense to specify any exclude bits.
> + */
> + if (event->attr.exclude_user || event->attr.exclude_kernel
> + || event->attr.exclude_hv || event->attr.exclude_idle)
> + return -ENOENT;
> +
> + /* Sampling not supported yet */
> + if (hwc->sample_period)
> + return -EINVAL;
Don't we need a "is root" check here? uncore counts everything, so
it cannot be limited to a single process.
> +static void uncore_pmu_cpu_starting(int cpu)
> +{
> + struct cpu_uncore_events *cpuc = &per_cpu(cpu_uncore_events, cpu);
> + struct intel_uncore *uncore;
> + int i, uncore_id;
> +
> + if (boot_cpu_data.x86_max_cores < 2)
> + return;
Why that check? uncore counting should work on a single core system too.
I think you should remove all of those.
> +
> + uncore_id = topology_physical_package_id(cpu);
> + WARN_ON_ONCE(uncore_id == BAD_APICID);
> +
> + raw_spin_lock(&intel_uncore_lock);
Does this really need to be a raw spinlock?
> +#define NHM_MSR_UNCORE_PERF_GLOBAL_CTRL 0x391
> +#define NHM_MSR_UNCORE_PMC0 0x3b0
> +#define NHM_MSR_UNCORE_PERFEVTSEL0 0x3c0
These should be in msr-index.h
-Andi
--
ak@linux.intel.com -- Speaking for myself only.
next prev parent reply other threads:[~2011-06-30 16:58 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-06-30 8:09 [PATCH 0/4] perf: Intel uncore pmu counting support Lin Ming
2011-06-30 8:09 ` [PATCH 1/4] perf, x86: Add Intel Nehalem/Westmere uncore pmu Lin Ming
2011-06-30 14:08 ` Peter Zijlstra
2011-07-01 6:05 ` Lin Ming
2011-06-30 16:58 ` Andi Kleen [this message]
2011-07-04 6:39 ` Lin Ming
2011-07-04 8:38 ` Peter Zijlstra
2011-07-04 21:57 ` Andi Kleen
2011-07-05 11:22 ` Peter Zijlstra
2011-07-05 12:48 ` Lin Ming
2011-07-05 12:56 ` Peter Zijlstra
2011-07-05 13:13 ` Lin Ming
2011-07-05 16:01 ` Andi Kleen
2011-07-06 9:35 ` Ingo Molnar
2011-06-30 8:09 ` [PATCH 2/4] perf, x86: Add Intel SandyBridge " Lin Ming
2011-06-30 22:09 ` Peter Zijlstra
2011-06-30 8:09 ` [PATCH 3/4] perf: Remove perf_event_attr::type check Lin Ming
2011-07-21 19:31 ` [tip:perf/core] " tip-bot for Lin Ming
2011-06-30 8:09 ` [PATCH 4/4] perf tool: Get PMU type id from sysfs Lin Ming
2011-06-30 12:10 ` [PATCH 0/4] perf: Intel uncore pmu counting support Stephane Eranian
2011-06-30 14:10 ` Peter Zijlstra
2011-06-30 16:27 ` Stephane Eranian
2011-07-01 3:17 ` Lin Ming
2011-07-01 10:49 ` Stephane Eranian
2011-07-01 12:23 ` Stephane Eranian
2011-07-01 12:28 ` Stephane Eranian
2011-07-04 6:03 ` Lin Ming
2011-07-01 5:49 ` Lin Ming
2011-07-01 11:08 ` Ingo Molnar
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