From: Don Zickus <dzickus@redhat.com>
To: Ingo Molnar <mingo@elte.hu>
Cc: Peter Zijlstra <peterz@infradead.org>,
Robert Richter <robert.richter@amd.com>,
Arnaldo Carvalho de Melo <acme@redhat.com>,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 4/7] perf, x86: Implement IBS interrupt handler
Date: Fri, 5 Aug 2011 09:47:48 -0400 [thread overview]
Message-ID: <20110805134748.GK1972@redhat.com> (raw)
In-Reply-To: <20110805095519.GC2420@elte.hu>
On Fri, Aug 05, 2011 at 11:55:19AM +0200, Ingo Molnar wrote:
> > I tried looking into but everytime I applied workarounds for Intel
> > errata I wound up with more unknown NMIs and proving that a couple
> > of them worked (with trace_printks) seemed elusive. I got
> > frustrated and left it alone.
> >
> > But yeah, Intel's perf has so many errata that I think if you kick
> > the box while running perf you can generate an unknown NMI.
>
> Hence the only sane approach is to just tolerate spurious NMIs and
> only annoy the user with them if there's *way* too many of them or
> so.
That may work if we can determine if the user is running perf or not. But
on older systems (like pre-Nehalem), sometimes the only way a system can
signal a platform error is through a single unknown NMI. I would be
afraid we might lose one of those if we 'tolerate' unknown NMIs.
So far I have only noticed perf generating 'unknown NMIs' on high volume
usage (like multiple counters). For the casual user it has been ok so
far.
Cheers,
Don
next prev parent reply other threads:[~2011-08-05 13:48 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-07-28 13:46 [PATCH 0/7] perf, x86: Implement AMD IBS Robert Richter
2011-07-28 13:46 ` [PATCH 1/7] perf, x86: share IBS macros between perf and oprofile Robert Richter
2011-07-28 13:46 ` [PATCH 2/7] perf, x86: Implement IBS initialization Robert Richter
2011-07-29 16:58 ` Peter Zijlstra
2011-08-01 5:27 ` Robert Richter
2011-08-02 11:49 ` Peter Zijlstra
2011-08-12 17:49 ` Robert Richter
2011-07-28 13:46 ` [PATCH 3/7] perf, x86: Implement IBS event configuration Robert Richter
2011-08-02 11:35 ` Peter Zijlstra
2011-08-12 19:51 ` Robert Richter
2011-07-28 13:46 ` [PATCH 4/7] perf, x86: Implement IBS interrupt handler Robert Richter
2011-07-29 16:58 ` Peter Zijlstra
2011-08-01 5:32 ` Robert Richter
2011-08-01 15:21 ` Peter Zijlstra
2011-08-01 16:38 ` Don Zickus
2011-08-05 9:55 ` Ingo Molnar
2011-08-05 13:47 ` Don Zickus [this message]
2011-08-02 11:43 ` Peter Zijlstra
2011-08-12 18:07 ` Robert Richter
2011-07-28 13:46 ` [PATCH 5/7] perf, x86: Implement IBS pmu control ops Robert Richter
2011-07-28 13:46 ` [PATCH 6/7] perf, x86: Example code for AMD IBS Robert Richter
2011-07-29 16:58 ` Peter Zijlstra
2011-08-01 5:50 ` Robert Richter
2011-08-02 10:37 ` Peter Zijlstra
2011-08-03 8:27 ` Michael Cree
2011-08-03 17:56 ` Robert Richter
2011-07-28 13:46 ` [PATCH 7/7] perf, x86: Implement 64 bit counter support for IBS Robert Richter
2011-07-29 16:58 ` Peter Zijlstra
2011-07-29 17:02 ` Peter Zijlstra
2011-08-01 5:55 ` Robert Richter
2011-07-29 17:01 ` Peter Zijlstra
2011-08-01 6:13 ` Robert Richter
2011-08-02 11:37 ` Peter Zijlstra
2011-08-12 18:11 ` Robert Richter
2011-07-29 17:07 ` [PATCH 0/7] perf, x86: Implement AMD IBS Peter Zijlstra
2011-08-01 5:21 ` Robert Richter
2011-08-02 11:29 ` Peter Zijlstra
2011-08-12 19:43 ` Robert Richter
2011-08-16 21:05 ` Robert Richter
-- strict thread matches above, loose matches on Subject: below --
2011-09-07 16:36 [PATCH 0/7 -v2] " Robert Richter
2011-09-07 16:36 ` [PATCH 4/7] perf, x86: Implement IBS interrupt handler Robert Richter
2011-09-14 16:13 ` Peter Zijlstra
2011-09-21 8:39 ` Robert Richter
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