Re: [V3][PATCH 4/7] perf, x86: Implement IBS interrupt handler

[Robert Richter <robert.richter@amd.com>]

On 22.09.11 17:51:34, Andi Kleen wrote:
> Robert Richter <robert.richter@amd.com> writes:
> >  
> > +static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
> > +{
> > +	struct perf_event *event = NULL;
> > +	struct hw_perf_event *hwc = &event->hw;
> > +	struct perf_sample_data data;
> > +	struct perf_raw_record raw;
> > +	struct pt_regs regs;
> > +	struct perf_ibs_data ibs_data;
> > +	int offset, size;
> > +	unsigned int msr;
> > +	u64 *buf;
> > +
> > +	msr = hwc->config_base;
> > +	buf = ibs_data.regs;
> > +	rdmsrl(msr, *buf);
> > +	if (!(*buf++ & perf_ibs->valid_mask))
> > +		return 0;
> 
> No check if the NMI is really caused by IBS? Very nasty.
> This will not interoperate well with other NMIs.

This is the check. If the valid bit is set in the config base msr,
then the nmi was caused by ibs. The function returns the number of
handled counters.

There is some more logic in the next patch that prevents reading the
msr if ibs is disabled.

-Robert

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Advanced Micro Devices, Inc.
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