From: Robert Richter <robert.richter@amd.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@elte.hu>,
Stephane Eranian <eranian@google.com>,
LKML <linux-kernel@vger.kernel.org>,
Don Zickus <dzickus@redhat.com>
Subject: Re: [V3][PATCH 0/7] perf, x86: Implement AMD IBS
Date: Fri, 23 Sep 2011 14:20:14 +0200 [thread overview]
Message-ID: <20110923122014.GP6063@erda.amd.com> (raw)
In-Reply-To: <1316778523.9084.17.camel@twins>
On 23.09.11 07:48:43, Peter Zijlstra wrote:
> There was also the thing about putting perf_event_set_period() and
> perf_event_try_update() in a common library and converting all pmu
> implementations to use them.
>
> As well as the for_each_set_bit_continue() thing which you've got
> queued.
Yeah, I will post separate patches for this.
> Anyway, I read through the stuff and it looks about right, so I'll wait
> for Don to post his NMI infrastructure bits once more (he had some
> pending changes) and then I'll queue this on top.
Many thanks.
> The only thing I'm not quite sure on is the userspace bits, but those
> are in the future work section as well, but possibly Ingo has a strong
> opinion here, sadly he doesn't have email atm :/
With Lin's patch 'perf: Remove perf_event_attr::type check' we already
can sample with perf record.
I think we could extend perf report to parse also ibs samples. The
only thing we need for it should be the pmu name/type mapping in the
perf.data header and the pmu type in the sample. See my comment on
Stephane's patch '[PATCH] perf: make perf.data more self-descriptive
(v5)'.
Thanks,
-Robert
--
Advanced Micro Devices, Inc.
Operating System Research Center
next prev parent reply other threads:[~2011-09-23 12:23 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-09-21 9:30 [V3][PATCH 0/7] perf, x86: Implement AMD IBS Robert Richter
2011-09-21 9:30 ` [V3][PATCH 1/7] perf, x86: share IBS macros between perf and oprofile Robert Richter
2011-09-21 9:30 ` [V3][PATCH 2/7] perf, x86: Implement IBS initialization Robert Richter
2011-09-21 9:30 ` [V3][PATCH 3/7] perf, x86: Implement IBS event configuration Robert Richter
2011-09-21 9:30 ` [V3][PATCH 4/7] perf, x86: Implement IBS interrupt handler Robert Richter
2011-09-22 21:51 ` Andi Kleen
2011-09-23 8:44 ` Robert Richter
2011-09-21 9:30 ` [V3][PATCH 5/7] perf, x86: Implement IBS pmu control ops Robert Richter
2011-09-21 9:30 ` [V3][PATCH 6/7] perf, x86: Implement 64 bit counter support for IBS Robert Richter
2011-09-21 9:30 ` [V3][PATCH 7/7] perf, x86: Example code for AMD IBS Robert Richter
2011-09-23 11:48 ` [V3][PATCH 0/7] perf, x86: Implement " Peter Zijlstra
2011-09-23 12:20 ` Robert Richter [this message]
2011-09-23 22:28 ` Andi Kleen
2011-09-25 15:20 ` David Ahern
2011-09-25 15:26 ` Andi Kleen
2011-09-25 15:29 ` David Ahern
2011-10-04 12:35 ` Stephane Eranian
2011-10-04 13:18 ` Andi Kleen
2011-10-04 13:20 ` Stephane Eranian
2011-10-04 8:27 ` Peter Zijlstra
2011-10-04 8:54 ` Ingo Molnar
2011-10-04 14:26 ` Robert Richter
2011-10-10 14:48 ` Robert Richter
2011-10-12 7:04 ` Ingo Molnar
2011-10-04 16:41 ` Andi Kleen
2011-10-04 16:45 ` Peter Zijlstra
2011-10-04 17:16 ` Robert Richter
2011-10-04 17:42 ` Andi Kleen
2011-10-10 6:05 ` Ingo Molnar
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