From: Gleb Natapov <gleb@redhat.com>
To: Avi Kivity <avi@redhat.com>
Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
joerg.roedel@amd.com, mingo@elte.hu, a.p.zijlstra@chello.nl
Subject: Re: [PATCH 6/9] perf, intel: Use GO/HO bits in perf-ctr
Date: Mon, 3 Oct 2011 17:41:13 +0200 [thread overview]
Message-ID: <20111003154113.GB3225@redhat.com> (raw)
In-Reply-To: <4E89CF73.4020208@redhat.com>
On Mon, Oct 03, 2011 at 05:06:27PM +0200, Avi Kivity wrote:
> On 10/03/2011 03:49 PM, Gleb Natapov wrote:
> >Intel does not have guest/host-only bit in perf counters like AMD
> >does. To support GO/HO bits KVM needs to switch EVENTSELn values
> >(or PERF_GLOBAL_CTRL if available) at a guest entry. If a counter is
> >configured to count only in a guest mode it stays disabled in a host,
> >but VMX is configured to switch it to enabled value during guest entry.
> >
> >This patch adds GO/HO tracking to Intel perf code and provides interface
> >for KVM to get a list of MSRs that need to be switched on a guest entry.
> >
> >Only cpus with architectural PMU (v1 or later) are supported with this
> >patch. To my knowledge there is not p6 models with VMX but without
> >architectural PMU and p4 with VMX are rare and the interface is general
> >enough to support them if need arise.
> >
> >+
> >+static int core_guest_get_msrs(int cnt, struct perf_guest_switch_msr *arr)
> >+{
> >+ struct cpu_hw_events *cpuc =&__get_cpu_var(cpu_hw_events);
> >+ int idx;
> >+
> >+ if (cnt< x86_pmu.num_counters)
> >+ return -ENOMEM;
> >+
> >+ for (idx = 0; idx< x86_pmu.num_counters; idx++) {
> >+ struct perf_event *event = cpuc->events[idx];
> >+
> >+ arr[idx].msr = x86_pmu_config_addr(idx);
> >+ arr[idx].host = arr[idx].guest = 0;
> >+
> >+ if (!test_bit(idx, cpuc->active_mask))
> >+ continue;
> >+
> >+ arr[idx].host = arr[idx].guest =
> >+ event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
> >+
> >+ if (event->attr.exclude_host)
> >+ arr[idx].host&= ~ARCH_PERFMON_EVENTSEL_ENABLE;
> >+ else if (event->attr.exclude_guest)
> >+ arr[idx].guest&= ~ARCH_PERFMON_EVENTSEL_ENABLE;
> >+ }
> >+
> >+ return 0;
> >+}
>
> Would be better to calculate these when the host msrs are
> calculated, instead of here, every vmentry.
>
For arch PMU v2 and greater it is precalculated. For v1 (which is almost
non existent, even my oldest cpu with VMX has v2 PMU) I am not sure it
will help since we need to copy information to perf_guest_switch_msr
array anyway here.
--
Gleb.
next prev parent reply other threads:[~2011-10-03 15:41 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-10-03 13:49 [PATCH 0/9] perf support for x86 guest/host-only bits Gleb Natapov
2011-10-03 13:49 ` [PATCH 1/9] perf, core: Introduce attrs to count in either host or guest mode Gleb Natapov
2011-10-03 13:49 ` [PATCH 2/9] perf, amd: Use GO/HO bits in perf-ctr Gleb Natapov
2011-10-03 13:49 ` [PATCH 3/9] perf, tools: Add support for guest/host-only profiling Gleb Natapov
2011-10-03 13:49 ` [PATCH 4/9] perf, tools: Fix copy&paste error in perf-kvm option description Gleb Natapov
2011-10-03 13:49 ` [PATCH 5/9] perf, tools: Do guest-only counting in perf-kvm by default Gleb Natapov
2011-10-03 13:49 ` [PATCH 6/9] perf, intel: Use GO/HO bits in perf-ctr Gleb Natapov
2011-10-03 15:06 ` Avi Kivity
2011-10-03 15:41 ` Gleb Natapov [this message]
2011-10-04 9:21 ` Avi Kivity
2011-10-03 13:49 ` [PATCH 7/9] KVM, VMX: add support for switching of PERF_GLOBAL_CTRL Gleb Natapov
2011-10-04 9:32 ` Avi Kivity
2011-10-04 9:57 ` Gleb Natapov
2011-10-03 13:49 ` [PATCH 8/9] KVM, VMX: Add support for guest/host-only profiling Gleb Natapov
2011-10-03 15:00 ` Avi Kivity
2011-10-03 15:36 ` Gleb Natapov
2011-10-04 9:28 ` Avi Kivity
2011-10-04 9:56 ` Gleb Natapov
2011-10-04 11:10 ` Avi Kivity
2011-10-04 11:17 ` Gleb Natapov
2011-10-04 11:24 ` Avi Kivity
2011-10-04 12:12 ` Gleb Natapov
2011-10-03 13:49 ` [PATCH 9/9] KVM, VMX: Check for automatic switch msr table overflow Gleb Natapov
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