* [PATCH 1/3] ASoC: wm8940: Fix setting PLL Output clock division ratio
@ 2011-10-24 3:32 Axel Lin
2011-10-24 3:33 ` [PATCH 2/3] ASoC: wm8940: Fix a typo for the mask of setting WM8940_BCLKDIV Axel Lin
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Axel Lin @ 2011-10-24 3:32 UTC (permalink / raw)
To: linux-kernel; +Cc: Mark Brown, Dimitris Papastamos, Liam Girdwood, alsa-devel
According to the datasheet:
The PLL Output clock division ratio is controlled by BIT[5:4] of
WM8940_GPIO register(08h).
Current code read/write the WM8940_ADDCNTRL(07h) register which is wrong.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
---
sound/soc/codecs/wm8940.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/sound/soc/codecs/wm8940.c b/sound/soc/codecs/wm8940.c
index a4abfdf..3cc3bce 100644
--- a/sound/soc/codecs/wm8940.c
+++ b/sound/soc/codecs/wm8940.c
@@ -627,8 +627,8 @@ static int wm8940_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
ret = snd_soc_write(codec, WM8940_CLOCK, reg | (div << 5));
break;
case WM8940_OPCLKDIV:
- reg = snd_soc_read(codec, WM8940_ADDCNTRL) & 0xFFCF;
- ret = snd_soc_write(codec, WM8940_ADDCNTRL, reg | (div << 4));
+ reg = snd_soc_read(codec, WM8940_GPIO) & 0xFFCF;
+ ret = snd_soc_write(codec, WM8940_GPIO, reg | (div << 4));
break;
}
return ret;
--
1.7.5.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/3] ASoC: wm8940: Fix a typo for the mask of setting WM8940_BCLKDIV
2011-10-24 3:32 [PATCH 1/3] ASoC: wm8940: Fix setting PLL Output clock division ratio Axel Lin
@ 2011-10-24 3:33 ` Axel Lin
2011-10-24 12:06 ` Girdwood, Liam
2011-10-24 3:35 ` [RFC][PATCH 3/3] ASoC: wm8940: Do not left shift the div parameter in wm8940_set_dai_clkdiv Axel Lin
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Axel Lin @ 2011-10-24 3:33 UTC (permalink / raw)
To: linux-kernel; +Cc: Mark Brown, Dimitris Papastamos, Liam Girdwood, alsa-devel
The registers are 16 bits, thus remove an extra F for the mask.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
---
sound/soc/codecs/wm8940.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/sound/soc/codecs/wm8940.c b/sound/soc/codecs/wm8940.c
index 3cc3bce..fec3892 100644
--- a/sound/soc/codecs/wm8940.c
+++ b/sound/soc/codecs/wm8940.c
@@ -619,7 +619,7 @@ static int wm8940_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
switch (div_id) {
case WM8940_BCLKDIV:
- reg = snd_soc_read(codec, WM8940_CLOCK) & 0xFFEF3;
+ reg = snd_soc_read(codec, WM8940_CLOCK) & 0xFEF3;
ret = snd_soc_write(codec, WM8940_CLOCK, reg | (div << 2));
break;
case WM8940_MCLKDIV:
--
1.7.5.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [RFC][PATCH 3/3] ASoC: wm8940: Do not left shift the div parameter in wm8940_set_dai_clkdiv
2011-10-24 3:32 [PATCH 1/3] ASoC: wm8940: Fix setting PLL Output clock division ratio Axel Lin
2011-10-24 3:33 ` [PATCH 2/3] ASoC: wm8940: Fix a typo for the mask of setting WM8940_BCLKDIV Axel Lin
@ 2011-10-24 3:35 ` Axel Lin
2011-10-24 10:10 ` Mark Brown
2011-10-24 12:06 ` [PATCH 1/3] ASoC: wm8940: Fix setting PLL Output clock division ratio Girdwood, Liam
2011-10-24 12:09 ` Mark Brown
3 siblings, 1 reply; 7+ messages in thread
From: Axel Lin @ 2011-10-24 3:35 UTC (permalink / raw)
To: linux-kernel; +Cc: Mark Brown, Dimitris Papastamos, Liam Girdwood, alsa-devel
Just check with other codec drivers, we do left shit div for
the corresponding bits from the caller in all other drivers.
I don't find the caller calling wm8940_set_dai_clkdiv now,
just make the behavior consistent with other drivers.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
---
sound/soc/codecs/wm8940.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/sound/soc/codecs/wm8940.c b/sound/soc/codecs/wm8940.c
index fec3892..72cec5b 100644
--- a/sound/soc/codecs/wm8940.c
+++ b/sound/soc/codecs/wm8940.c
@@ -620,15 +620,15 @@ static int wm8940_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
switch (div_id) {
case WM8940_BCLKDIV:
reg = snd_soc_read(codec, WM8940_CLOCK) & 0xFEF3;
- ret = snd_soc_write(codec, WM8940_CLOCK, reg | (div << 2));
+ ret = snd_soc_write(codec, WM8940_CLOCK, reg | div);
break;
case WM8940_MCLKDIV:
reg = snd_soc_read(codec, WM8940_CLOCK) & 0xFF1F;
- ret = snd_soc_write(codec, WM8940_CLOCK, reg | (div << 5));
+ ret = snd_soc_write(codec, WM8940_CLOCK, reg | div);
break;
case WM8940_OPCLKDIV:
reg = snd_soc_read(codec, WM8940_GPIO) & 0xFFCF;
- ret = snd_soc_write(codec, WM8940_GPIO, reg | (div << 4));
+ ret = snd_soc_write(codec, WM8940_GPIO, reg | div);
break;
}
return ret;
--
1.7.5.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [RFC][PATCH 3/3] ASoC: wm8940: Do not left shift the div parameter in wm8940_set_dai_clkdiv
2011-10-24 3:35 ` [RFC][PATCH 3/3] ASoC: wm8940: Do not left shift the div parameter in wm8940_set_dai_clkdiv Axel Lin
@ 2011-10-24 10:10 ` Mark Brown
0 siblings, 0 replies; 7+ messages in thread
From: Mark Brown @ 2011-10-24 10:10 UTC (permalink / raw)
To: Axel Lin; +Cc: linux-kernel, Dimitris Papastamos, Liam Girdwood, alsa-devel
On Mon, Oct 24, 2011 at 11:35:12AM +0800, Axel Lin wrote:
> Just check with other codec drivers, we do left shit div for
> the corresponding bits from the caller in all other drivers.
> I don't find the caller calling wm8940_set_dai_clkdiv now,
> just make the behavior consistent with other drivers.
The semantics for the clkdivs are entirely defined by the individual
drivers - there's no actual standard here and I guess this may break
some out of tree machines that people have. If we're going to a cleanup
here it'd be better to improve the driver to figure out the divider
configurations automatically as far as possible.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/3] ASoC: wm8940: Fix setting PLL Output clock division ratio
2011-10-24 3:32 [PATCH 1/3] ASoC: wm8940: Fix setting PLL Output clock division ratio Axel Lin
2011-10-24 3:33 ` [PATCH 2/3] ASoC: wm8940: Fix a typo for the mask of setting WM8940_BCLKDIV Axel Lin
2011-10-24 3:35 ` [RFC][PATCH 3/3] ASoC: wm8940: Do not left shift the div parameter in wm8940_set_dai_clkdiv Axel Lin
@ 2011-10-24 12:06 ` Girdwood, Liam
2011-10-24 12:09 ` Mark Brown
3 siblings, 0 replies; 7+ messages in thread
From: Girdwood, Liam @ 2011-10-24 12:06 UTC (permalink / raw)
To: Axel Lin; +Cc: linux-kernel, Mark Brown, Dimitris Papastamos, alsa-devel
On 24 October 2011 04:32, Axel Lin <axel.lin@gmail.com> wrote:
> According to the datasheet:
> The PLL Output clock division ratio is controlled by BIT[5:4] of
> WM8940_GPIO register(08h).
> Current code read/write the WM8940_ADDCNTRL(07h) register which is wrong.
>
> Signed-off-by: Axel Lin <axel.lin@gmail.com>
> ---
> sound/soc/codecs/wm8940.c | 4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/sound/soc/codecs/wm8940.c b/sound/soc/codecs/wm8940.c
> index a4abfdf..3cc3bce 100644
> --- a/sound/soc/codecs/wm8940.c
> +++ b/sound/soc/codecs/wm8940.c
> @@ -627,8 +627,8 @@ static int wm8940_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
> ret = snd_soc_write(codec, WM8940_CLOCK, reg | (div << 5));
> break;
> case WM8940_OPCLKDIV:
> - reg = snd_soc_read(codec, WM8940_ADDCNTRL) & 0xFFCF;
> - ret = snd_soc_write(codec, WM8940_ADDCNTRL, reg | (div << 4));
> + reg = snd_soc_read(codec, WM8940_GPIO) & 0xFFCF;
> + ret = snd_soc_write(codec, WM8940_GPIO, reg | (div << 4));
> break;
> }
> return ret;
> --
Acked-by: Liam Girdwood <lrg@ti.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/3] ASoC: wm8940: Fix a typo for the mask of setting WM8940_BCLKDIV
2011-10-24 3:33 ` [PATCH 2/3] ASoC: wm8940: Fix a typo for the mask of setting WM8940_BCLKDIV Axel Lin
@ 2011-10-24 12:06 ` Girdwood, Liam
0 siblings, 0 replies; 7+ messages in thread
From: Girdwood, Liam @ 2011-10-24 12:06 UTC (permalink / raw)
To: Axel Lin; +Cc: linux-kernel, Mark Brown, Dimitris Papastamos, alsa-devel
On 24 October 2011 04:33, Axel Lin <axel.lin@gmail.com> wrote:
> The registers are 16 bits, thus remove an extra F for the mask.
>
> Signed-off-by: Axel Lin <axel.lin@gmail.com>
> ---
> sound/soc/codecs/wm8940.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/sound/soc/codecs/wm8940.c b/sound/soc/codecs/wm8940.c
> index 3cc3bce..fec3892 100644
> --- a/sound/soc/codecs/wm8940.c
> +++ b/sound/soc/codecs/wm8940.c
> @@ -619,7 +619,7 @@ static int wm8940_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
>
> switch (div_id) {
> case WM8940_BCLKDIV:
> - reg = snd_soc_read(codec, WM8940_CLOCK) & 0xFFEF3;
> + reg = snd_soc_read(codec, WM8940_CLOCK) & 0xFEF3;
> ret = snd_soc_write(codec, WM8940_CLOCK, reg | (div << 2));
> break;
> case WM8940_MCLKDIV:
> --
Acked-by: Liam Girdwood <lrg@ti.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/3] ASoC: wm8940: Fix setting PLL Output clock division ratio
2011-10-24 3:32 [PATCH 1/3] ASoC: wm8940: Fix setting PLL Output clock division ratio Axel Lin
` (2 preceding siblings ...)
2011-10-24 12:06 ` [PATCH 1/3] ASoC: wm8940: Fix setting PLL Output clock division ratio Girdwood, Liam
@ 2011-10-24 12:09 ` Mark Brown
3 siblings, 0 replies; 7+ messages in thread
From: Mark Brown @ 2011-10-24 12:09 UTC (permalink / raw)
To: Axel Lin; +Cc: linux-kernel, Dimitris Papastamos, Liam Girdwood, alsa-devel
On Mon, Oct 24, 2011 at 11:32:41AM +0800, Axel Lin wrote:
> According to the datasheet:
> The PLL Output clock division ratio is controlled by BIT[5:4] of
> WM8940_GPIO register(08h).
> Current code read/write the WM8940_ADDCNTRL(07h) register which is wrong.
Applied this and patch 2, thanks.
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2011-10-24 12:09 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2011-10-24 3:32 [PATCH 1/3] ASoC: wm8940: Fix setting PLL Output clock division ratio Axel Lin
2011-10-24 3:33 ` [PATCH 2/3] ASoC: wm8940: Fix a typo for the mask of setting WM8940_BCLKDIV Axel Lin
2011-10-24 12:06 ` Girdwood, Liam
2011-10-24 3:35 ` [RFC][PATCH 3/3] ASoC: wm8940: Do not left shift the div parameter in wm8940_set_dai_clkdiv Axel Lin
2011-10-24 10:10 ` Mark Brown
2011-10-24 12:06 ` [PATCH 1/3] ASoC: wm8940: Fix setting PLL Output clock division ratio Girdwood, Liam
2011-10-24 12:09 ` Mark Brown
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