From: Mark Brown <broonie@opensource.wolfsonmicro.com>
To: Axel Lin <axel.lin@gmail.com>
Cc: linux-kernel@vger.kernel.org,
Dimitris Papastamos <dp@opensource.wolfsonmicro.com>,
Liam Girdwood <lrg@ti.com>,
alsa-devel@alsa-project.org
Subject: Re: [PATCH 1/3] ASoC: wm8940: Fix setting PLL Output clock division ratio
Date: Mon, 24 Oct 2011 14:09:07 +0200 [thread overview]
Message-ID: <20111024120907.GG6148@opensource.wolfsonmicro.com> (raw)
In-Reply-To: <1319427161.5773.3.camel@phoenix>
On Mon, Oct 24, 2011 at 11:32:41AM +0800, Axel Lin wrote:
> According to the datasheet:
> The PLL Output clock division ratio is controlled by BIT[5:4] of
> WM8940_GPIO register(08h).
> Current code read/write the WM8940_ADDCNTRL(07h) register which is wrong.
Applied this and patch 2, thanks.
prev parent reply other threads:[~2011-10-24 12:09 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-10-24 3:32 [PATCH 1/3] ASoC: wm8940: Fix setting PLL Output clock division ratio Axel Lin
2011-10-24 3:33 ` [PATCH 2/3] ASoC: wm8940: Fix a typo for the mask of setting WM8940_BCLKDIV Axel Lin
2011-10-24 12:06 ` Girdwood, Liam
2011-10-24 3:35 ` [RFC][PATCH 3/3] ASoC: wm8940: Do not left shift the div parameter in wm8940_set_dai_clkdiv Axel Lin
2011-10-24 10:10 ` Mark Brown
2011-10-24 12:06 ` [PATCH 1/3] ASoC: wm8940: Fix setting PLL Output clock division ratio Girdwood, Liam
2011-10-24 12:09 ` Mark Brown [this message]
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