From: Andreas Herrmann <andreas.herrmann3@amd.com>
To: Ingo Molnar <mingo@elte.hu>
Cc: <linux-tip-commits@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <hpa@zytor.com>,
<mingo@redhat.com>, <davej@redhat.com>, <Borislav.Petkov@amd.com>,
<stable@kernel.org>, <tglx@linutronix.de>
Subject: Re: [tip:x86/urgent] x86/amd: Fix L1i and L2 cache sharing information for AMD family 15h processors
Date: Thu, 9 Feb 2012 16:35:33 +0100 [thread overview]
Message-ID: <20120209153533.GG30341@alberich.amd.com> (raw)
In-Reply-To: <20120209133754.GA12584@elte.hu>
On Thu, Feb 09, 2012 at 02:37:54PM +0100, Ingo Molnar wrote:
>
> This commit seems to cause a boot hang on an old Athlon64 CPU:
Are you sure that it's this commit, or is it possible that some other
patch in tip might trigger the trouble? (Systems boots fine with this
patch reverted?)
> CPU: Physical Processor ID: 0
> CPU: Processor Core ID: 0
> numa_add_cpu cpu 0 node 0: mask now 0
> ExtINT not setup in hardware but reported by MP table
> ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=0 pin2=0
> ..MP-BIOS bug: 8254 timer not connected to IO-APIC
> ...trying to set up timer (IRQ0) through the 8259A ...
> ..... (found apic 0 pin 0) ...
> ....... works.
> CPU0: AMD Athlon(tm) 64 X2 Dual Core Processor 3800+ stepping 02
Can't reproduce this here (tried it on a couple of further
systems). Can you please provide dmesg or at least /proc/cpuinfo
output? (Also at the moment, it's not obvious to me how this timer
interrupt trouble is related to this patch.)
Thanks,
Andreas
next prev parent reply other threads:[~2012-02-09 15:35 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-02-08 19:52 [PATCH] x86/amd: Fix L1i and L2 cache sharing information for AMD family 15h processors Andreas Herrmann
2012-02-09 12:41 ` [tip:x86/urgent] " tip-bot for Andreas Herrmann
2012-02-09 13:37 ` Ingo Molnar
2012-02-09 15:35 ` Andreas Herrmann [this message]
2012-02-10 6:17 ` Ingo Molnar
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