[PATCH 0/4] Some fixes over the last EDAC series

[PATCH 0/4] Some fixes over the last EDAC series

[Mauro Carvalho Chehab]

This patch series contains a few bug fixes/regressions introduced by
my patch series.

There are two trivial bug fixes for i5100/i3200 drivers. It also contains
a bug fix for amd64_edac, as commented at the ML.

The bigger patch here is the one that will print "rank" instead of "dimm"
for the debug messages. This patch complements the patch 5/6 of the previous
series [1], as discussed.

[1] http://lkml.org/lkml/2012/3/7/174

I may fold those patches when submitting my git tree to Linus, but
it is better to keep them as incremental patches for the reviewers to
not need to review the entire patch series again.

The tree with this patches (and the previous ones) is available (after
kernel.org mirror sync) at:
	git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac.git hw_events_v7

Mauro Carvalho Chehab (4):
  i3200_edac: Fix a regression introduced by 3b6909b
  edac: display "rank" for csrow-based MC's at the debug msgs
  amd64_edac: Fix the rank number of pages count
  i5100_edac: Fix a warning on a debug message

 drivers/edac/amd64_edac.c    |    2 +-
 drivers/edac/edac_mc.c       |   43 +++++++++++++++++++++++++++++------------
 drivers/edac/edac_mc_sysfs.c |   19 ++++-------------
 drivers/edac/i3200_edac.c    |    3 +-
 drivers/edac/i5100_edac.c    |    2 +-
 include/linux/edac.h         |   12 ++++++++++-
 6 files changed, 50 insertions(+), 31 deletions(-)

The amd64_edac driver is now properly reporting the memory ranks on
my test system (a 8 sockets/32 core system, equipped with 4 x 4GB 1R DIMMs):

# grep . /sys/devices/system/edac/mc/mc?/dimm*/* /sys/devices/system/edac/mc/mc?/rank*/*
grep: /sys/devices/system/edac/mc/mc?/dimm*/*: Arquivo ou diretório não encontrado
/sys/devices/system/edac/mc/mc0/rank4/dimm_dev_type:Unknown
/sys/devices/system/edac/mc/mc0/rank4/dimm_edac_mode:S4ECD4ED
/sys/devices/system/edac/mc/mc0/rank4/dimm_label:mc#0csrow#4channel#0
/sys/devices/system/edac/mc/mc0/rank4/dimm_location:csrow 4 channel 0 
/sys/devices/system/edac/mc/mc0/rank4/dimm_mem_type:Registered-DDR3
/sys/devices/system/edac/mc/mc0/rank4/dimm_size:4096
/sys/devices/system/edac/mc/mc2/rank4/dimm_dev_type:Unknown
/sys/devices/system/edac/mc/mc2/rank4/dimm_edac_mode:S4ECD4ED
/sys/devices/system/edac/mc/mc2/rank4/dimm_label:mc#2csrow#4channel#0
/sys/devices/system/edac/mc/mc2/rank4/dimm_location:csrow 4 channel 0 
/sys/devices/system/edac/mc/mc2/rank4/dimm_mem_type:Registered-DDR3
/sys/devices/system/edac/mc/mc2/rank4/dimm_size:4096
/sys/devices/system/edac/mc/mc4/rank4/dimm_dev_type:Unknown
/sys/devices/system/edac/mc/mc4/rank4/dimm_edac_mode:S4ECD4ED
/sys/devices/system/edac/mc/mc4/rank4/dimm_label:mc#4csrow#4channel#0
/sys/devices/system/edac/mc/mc4/rank4/dimm_location:csrow 4 channel 0 
/sys/devices/system/edac/mc/mc4/rank4/dimm_mem_type:Registered-DDR3
/sys/devices/system/edac/mc/mc4/rank4/dimm_size:4096
/sys/devices/system/edac/mc/mc7/rank4/dimm_dev_type:Unknown
/sys/devices/system/edac/mc/mc7/rank4/dimm_edac_mode:S4ECD4ED
/sys/devices/system/edac/mc/mc7/rank4/dimm_label:mc#7csrow#4channel#0
/sys/devices/system/edac/mc/mc7/rank4/dimm_location:csrow 4 channel 0 
/sys/devices/system/edac/mc/mc7/rank4/dimm_mem_type:Registered-DDR3
/sys/devices/system/edac/mc/mc7/rank4/dimm_size:4096

# dmesg|grep -i edac|grep MC:
[   37.462195] EDAC MC: Ver: 2.1.0
[   37.610622] EDAC MC: DCT0 chip selects:
[   37.610624] EDAC amd64: MC: 0:     0MB 1:     0MB
[   37.667756] EDAC amd64: MC: 2:     0MB 3:     0MB
[   37.700294] EDAC amd64: MC: 4:  4096MB 5:     0MB
[   37.732300] EDAC amd64: MC: 6:     0MB 7:     0MB
[   37.763833] EDAC MC: DCT1 chip selects:
[   37.763838] EDAC amd64: MC: 0:     0MB 1:     0MB
[   37.794506] EDAC amd64: MC: 2:     0MB 3:     0MB
[   37.862682] EDAC amd64: MC: 4:     0MB 5:     0MB
[   37.949646] EDAC amd64: MC: 6:     0MB 7:     0MB
[   38.624781] EDAC MC: DCT0 chip selects:
[   38.624782] EDAC amd64: MC: 0:     0MB 1:     0MB
[   38.656778] EDAC amd64: MC: 2:     0MB 3:     0MB
[   38.738786] EDAC amd64: MC: 4:     0MB 5:     0MB
[   38.773151] EDAC amd64: MC: 6:     0MB 7:     0MB
[   38.806202] EDAC MC: DCT1 chip selects:
[   38.806203] EDAC amd64: MC: 0:     0MB 1:     0MB
[   38.837650] EDAC amd64: MC: 2:     0MB 3:     0MB
[   38.869205] EDAC amd64: MC: 4:     0MB 5:     0MB
[   38.901188] EDAC amd64: MC: 6:     0MB 7:     0MB
[   39.865634] EDAC MC: DCT0 chip selects:
[   39.865639] EDAC amd64: MC: 0:     0MB 1:     0MB
[   39.897631] EDAC amd64: MC: 2:     0MB 3:     0MB
[   39.930204] EDAC amd64: MC: 4:  4096MB 5:     0MB
[   40.140835] EDAC amd64: MC: 6:     0MB 7:     0MB
[   40.140839] EDAC MC: DCT1 chip selects:
[   40.140841] EDAC amd64: MC: 0:     0MB 1:     0MB
[   40.140842] EDAC amd64: MC: 2:     0MB 3:     0MB
[   40.140844] EDAC amd64: MC: 4:     0MB 5:     0MB
[   40.140847] EDAC amd64: MC: 6:     0MB 7:     0MB
[   41.090571] EDAC MC: DCT0 chip selects:
[   41.090573] EDAC amd64: MC: 0:     0MB 1:     0MB
[   41.123284] EDAC amd64: MC: 2:     0MB 3:     0MB
[   41.154824] EDAC amd64: MC: 4:     0MB 5:     0MB
[   41.184975] EDAC amd64: MC: 6:     0MB 7:     0MB
[   41.215036] EDAC MC: DCT1 chip selects:
[   41.215038] EDAC amd64: MC: 0:     0MB 1:     0MB
[   41.246632] EDAC amd64: MC: 2:     0MB 3:     0MB
[   41.308208] EDAC amd64: MC: 4:     0MB 5:     0MB
[   41.399933] EDAC amd64: MC: 6:     0MB 7:     0MB
[   41.965913] EDAC MC: DCT0 chip selects:
[   41.965918] EDAC amd64: MC: 0:     0MB 1:     0MB
[   42.054599] EDAC amd64: MC: 2:     0MB 3:     0MB
[   42.129714] EDAC amd64: MC: 4:  4096MB 5:     0MB
[   42.163109] EDAC amd64: MC: 6:     0MB 7:     0MB
[   42.194608] EDAC MC: DCT1 chip selects:
[   42.194610] EDAC amd64: MC: 0:     0MB 1:     0MB
[   42.226118] EDAC amd64: MC: 2:     0MB 3:     0MB
[   42.226119] EDAC amd64: MC: 4:     0MB 5:     0MB
[   42.226121] EDAC amd64: MC: 6:     0MB 7:     0MB
[   42.610838] EDAC MC: DCT0 chip selects:
[   42.610843] EDAC amd64: MC: 0:     0MB 1:     0MB
[   42.709570] EDAC amd64: MC: 2:     0MB 3:     0MB
[   42.789579] EDAC amd64: MC: 4:     0MB 5:     0MB
[   42.881698] EDAC amd64: MC: 6:     0MB 7:     0MB
[   42.963611] EDAC MC: DCT1 chip selects:
[   42.963613] EDAC amd64: MC: 0:     0MB 1:     0MB
[   43.043573] EDAC amd64: MC: 2:     0MB 3:     0MB
[   43.128559] EDAC amd64: MC: 4:     0MB 5:     0MB
[   43.199141] EDAC amd64: MC: 6:     0MB 7:     0MB
[   43.519255] EDAC MC: DCT0 chip selects:
[   43.519257] EDAC amd64: MC: 0:     0MB 1:     0MB
[   43.550192] EDAC amd64: MC: 2:     0MB 3:     0MB
[   43.582120] EDAC amd64: MC: 4:     0MB 5:     0MB
[   43.613620] EDAC amd64: MC: 6:     0MB 7:     0MB
[   43.658514] EDAC MC: DCT1 chip selects:
[   43.658516] EDAC amd64: MC: 0:     0MB 1:     0MB
[   43.761584] EDAC amd64: MC: 2:     0MB 3:     0MB
[   43.850554] EDAC amd64: MC: 4:     0MB 5:     0MB
[   43.937551] EDAC amd64: MC: 6:     0MB 7:     0MB
[   44.486332] EDAC MC: DCT0 chip selects:
[   44.486337] EDAC amd64: MC: 0:     0MB 1:     0MB
[   44.540205] EDAC amd64: MC: 2:     0MB 3:     0MB
[   44.571106] EDAC amd64: MC: 4:  4096MB 5:     0MB
[   44.602915] EDAC amd64: MC: 6:     0MB 7:     0MB
[   44.602927] EDAC MC: DCT1 chip selects:
[   44.602931] EDAC amd64: MC: 0:     0MB 1:     0MB
[   44.602935] EDAC amd64: MC: 2:     0MB 3:     0MB
[   44.602939] EDAC amd64: MC: 4:     0MB 5:     0MB
[   44.602944] EDAC amd64: MC: 6:     0MB 7:     0MB

# dmesg|grep -i edac|grep rank
[   38.199552] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc(): allocating 5672 bytes for mci data (8 ranks, 8 csrows/channels)
[   38.199568] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 0: rank0 (0:0:0): row 0, chan 0
[   38.199573] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 1: rank1 (1:0:0): row 1, chan 0
[   38.199576] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 2: rank2 (2:0:0): row 2, chan 0
[   38.199579] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 3: rank3 (3:0:0): row 3, chan 0
[   38.199582] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 4: rank4 (4:0:0): row 4, chan 0
[   38.199585] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 5: rank5 (5:0:0): row 5, chan 0
[   38.199588] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 6: rank6 (6:0:0): row 6, chan 0
[   38.199591] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 7: rank7 (7:0:0): row 7, chan 0
[   39.038966] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc(): allocating 4392 bytes for mci data (8 ranks, 8 csrows/channels)
[   39.038981] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 0: rank0 (0:0:0): row 0, chan 0
[   39.038984] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 1: rank0 (1:0:0): row 1, chan 0
[   39.038987] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 2: rank0 (2:0:0): row 2, chan 0
[   39.038991] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 3: rank0 (3:0:0): row 3, chan 0
[   39.038994] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 4: rank0 (4:0:0): row 4, chan 0
[   39.038997] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 5: rank0 (5:0:0): row 5, chan 0
[   39.039000] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 6: rank0 (6:0:0): row 6, chan 0
[   39.039023] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 7: rank0 (7:0:0): row 7, chan 0
[   40.140865] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc(): allocating 5672 bytes for mci data (8 ranks, 8 csrows/channels)
[   40.140877] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 0: rank0 (0:0:0): row 0, chan 0
[   40.140881] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 1: rank1 (1:0:0): row 1, chan 0
[   40.140884] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 2: rank2 (2:0:0): row 2, chan 0
[   40.140887] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 3: rank3 (3:0:0): row 3, chan 0
[   40.140890] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 4: rank4 (4:0:0): row 4, chan 0
[   40.140893] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 5: rank5 (5:0:0): row 5, chan 0
[   40.140896] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 6: rank6 (6:0:0): row 6, chan 0
[   40.140898] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 7: rank7 (7:0:0): row 7, chan 0
[   41.668192] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc(): allocating 4392 bytes for mci data (8 ranks, 8 csrows/channels)
[   41.668200] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 0: rank0 (0:0:0): row 0, chan 0
[   41.668203] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 1: rank0 (1:0:0): row 1, chan 0
[   41.668207] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 2: rank0 (2:0:0): row 2, chan 0
[   41.668209] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 3: rank0 (3:0:0): row 3, chan 0
[   41.668212] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 4: rank0 (4:0:0): row 4, chan 0
[   41.668215] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 5: rank0 (5:0:0): row 5, chan 0
[   41.668218] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 6: rank0 (6:0:0): row 6, chan 0
[   41.668221] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 7: rank0 (7:0:0): row 7, chan 0
[   42.226144] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc(): allocating 5672 bytes for mci data (8 ranks, 8 csrows/channels)
[   42.226158] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 0: rank0 (0:0:0): row 0, chan 0
[   42.226163] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 1: rank1 (1:0:0): row 1, chan 0
[   42.226166] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 2: rank2 (2:0:0): row 2, chan 0
[   42.226169] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 3: rank3 (3:0:0): row 3, chan 0
[   42.226171] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 4: rank4 (4:0:0): row 4, chan 0
[   42.226174] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 5: rank5 (5:0:0): row 5, chan 0
[   42.226177] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 6: rank6 (6:0:0): row 6, chan 0
[   42.226180] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 7: rank7 (7:0:0): row 7, chan 0
[   43.378776] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc(): allocating 4392 bytes for mci data (8 ranks, 8 csrows/channels)
[   43.379391] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 0: rank0 (0:0:0): row 0, chan 0
[   43.379394] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 1: rank0 (1:0:0): row 1, chan 0
[   43.379397] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 2: rank0 (2:0:0): row 2, chan 0
[   43.379400] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 3: rank0 (3:0:0): row 3, chan 0
[   43.379403] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 4: rank0 (4:0:0): row 4, chan 0
[   43.379406] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 5: rank0 (5:0:0): row 5, chan 0
[   43.379409] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 6: rank0 (6:0:0): row 6, chan 0
[   43.379412] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 7: rank0 (7:0:0): row 7, chan 0
[   44.179524] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc(): allocating 4392 bytes for mci data (8 ranks, 8 csrows/channels)
[   44.179534] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 0: rank0 (0:0:0): row 0, chan 0
[   44.179537] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 1: rank0 (1:0:0): row 1, chan 0
[   44.179540] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 2: rank0 (2:0:0): row 2, chan 0
[   44.179543] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 3: rank0 (3:0:0): row 3, chan 0
[   44.179546] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 4: rank0 (4:0:0): row 4, chan 0
[   44.179549] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 5: rank0 (5:0:0): row 5, chan 0
[   44.179552] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 6: rank0 (6:0:0): row 6, chan 0
[   44.179555] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 7: rank0 (7:0:0): row 7, chan 0
[   44.602994] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc(): allocating 5672 bytes for mci data (8 ranks, 8 csrows/channels)
[   44.603030] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 0: rank0 (0:0:0): row 0, chan 0
[   44.603041] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 1: rank1 (1:0:0): row 1, chan 0
[   44.603050] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 2: rank2 (2:0:0): row 2, chan 0
[   44.603058] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 3: rank3 (3:0:0): row 3, chan 0
[   44.603067] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 4: rank4 (4:0:0): row 4, chan 0
[   44.603075] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 5: rank5 (5:0:0): row 5, chan 0
[   44.603084] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 6: rank6 (6:0:0): row 6, chan 0
[   44.603092] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 7: rank7 (7:0:0): row 7, chan 0

[PATCH 1/4] i3200_edac: Fix a regression introduced by 3b6909b

[Mauro Carvalho Chehab]

The size of the private data structure is not zero. Fix it.

This is a cut-and-paste error introduced when copying the alloc init
code from some other driver.

Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
---
 drivers/edac/i3200_edac.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/drivers/edac/i3200_edac.c b/drivers/edac/i3200_edac.c
index 1233435..9171823 100644
--- a/drivers/edac/i3200_edac.c
+++ b/drivers/edac/i3200_edac.c
@@ -358,7 +358,8 @@ static int i3200_probe1(struct pci_dev *pdev, int dev_idx)
 	layers[1].type = EDAC_MC_LAYER_CHANNEL;
 	layers[1].size = nr_channels;
 	layers[1].is_csrow = false;
-	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, false, 0);
+	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
+			    false, sizeof(struct i3200_priv));
 	if (!mci)
 		return -ENOMEM;
 
-- 
1.7.8

[PATCH 2/4] edac: display "rank" for csrow-based MC's at the debug msgs

[Mauro Carvalho Chehab]

This patch complements changeset 114ea60: on all places where the
struct dimm_info actually stores ranks, call it as "rank" at all
displayed messages.

Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
---
 drivers/edac/edac_mc.c       |   43 +++++++++++++++++++++++++++++------------
 drivers/edac/edac_mc_sysfs.c |   19 ++++-------------
 include/linux/edac.h         |   12 ++++++++++-
 3 files changed, 46 insertions(+), 28 deletions(-)

diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c
index e1589b6..ea5fec4 100644
--- a/drivers/edac/edac_mc.c
+++ b/drivers/edac/edac_mc.c
@@ -83,6 +83,8 @@ static void edac_mc_dump_csrow(struct csrow_info *csrow)
 
 static void edac_mc_dump_mci(struct mem_ctl_info *mci)
 {
+	const char *type = mci->mem_is_per_rank ? "ranks" : "dimms";
+
 	debugf3("\tmci = %p\n", mci);
 	debugf3("\tmci->mtype_cap = %lx\n", mci->mtype_cap);
 	debugf3("\tmci->edac_ctl_cap = %lx\n", mci->edac_ctl_cap);
@@ -90,8 +92,8 @@ static void edac_mc_dump_mci(struct mem_ctl_info *mci)
 	debugf4("\tmci->edac_check = %p\n", mci->edac_check);
 	debugf3("\tmci->num_csrows = %d, csrows = %p\n",
 		mci->num_csrows, mci->csrows);
-	debugf3("\tmci->nr_dimms = %d, dimns = %p\n",
-		mci->tot_dimms, mci->dimms);
+	debugf3("\tmci->nr_%s = %d, %s = %p\n",
+		type, mci->tot_dimms, type, mci->dimms);
 	debugf3("\tdev = %p\n", mci->dev);
 	debugf3("\tmod_name:ctl_name = %s:%s\n", mci->mod_name, mci->ctl_name);
 	debugf3("\tpvt_info = %p\n\n", mci->pvt_info);
@@ -171,10 +173,6 @@ void *edac_align_ptr(void **p, unsigned size, int quant)
  * @size_pvt:		size of private storage needed
  *
  *
- * FIXME: drivers handle multi-rank memories on different ways: on some
- * drivers, one multi-rank memory is mapped as one DIMM, while, on others,
- * a single multi-rank DIMM would be mapped into several "dimms".
- *
  * Non-csrow based drivers (like FB-DIMM and RAMBUS ones) will likely report
  * such DIMMS properly, but the CSROWS-based ones will likely do the wrong
  * thing, as two chip select values are used for dual-rank memories (and 4, for
@@ -189,6 +187,12 @@ void *edac_align_ptr(void **p, unsigned size, int quant)
  *
  * Use edac_mc_free() to free mc structures allocated by this function.
  *
+ * NOTE: drivers handle multi-rank memories on different ways: on some
+ * drivers, one multi-rank memory is mapped as one entry, while, on others,
+ * a single multi-rank DIMM would be mapped into several entries. Currently,
+ * this function will allocate multiple struct dimm_info on such scenarios,
+ * as grouping the multiple ranks require drivers change.
+ *
  * Returns:
  *	NULL allocation failed
  *	struct mem_ctl_info pointer
@@ -214,6 +218,7 @@ struct mem_ctl_info *edac_mc_alloc(unsigned edac_index,
 	int i, j, n, len;
 	int err;
 	int row, chn;
+	bool per_rank = false;
 
 	BUG_ON(n_layers > EDAC_MAX_LAYERS);
 	/*
@@ -229,6 +234,11 @@ struct mem_ctl_info *edac_mc_alloc(unsigned edac_index,
 			tot_csrows *= layers[i].size;
 		else
 			tot_cschannels *= layers[i].size;
+
+		if (layers[i].type == EDAC_MC_LAYER_CHIP_SELECT) {
+			per_rank = true;
+			break;
+		}
 	}
 
 	/* Figure out the offsets of the various items from the start of an mc
@@ -257,8 +267,11 @@ struct mem_ctl_info *edac_mc_alloc(unsigned edac_index,
 	pvt = edac_align_ptr(&ptr, sz_pvt, 1);
 	size = ((unsigned long)pvt) + sz_pvt;
 
-	debugf1("%s(): allocating %u bytes for mci data (%d dimms, %d csrows/channels)\n",
-		__func__, size, tot_dimms, tot_csrows * tot_cschannels);
+	debugf1("%s(): allocating %u bytes for mci data (%d %s, %d csrows/channels)\n",
+		__func__, size,
+		tot_dimms,
+		per_rank ? "ranks" : "dimms",
+		tot_csrows * tot_cschannels);
 	mci = kzalloc(size, GFP_KERNEL);
 	if (mci == NULL)
 		return NULL;
@@ -291,6 +304,7 @@ struct mem_ctl_info *edac_mc_alloc(unsigned edac_index,
 	memcpy(mci->layers, layers, sizeof(*lay) * n_layers);
 	mci->num_csrows = tot_csrows;
 	mci->num_cschannel = tot_cschannels;
+	mci->mem_is_per_rank = true;
 
 	/*
 	 * Fills the csrow struct
@@ -316,15 +330,16 @@ struct mem_ctl_info *edac_mc_alloc(unsigned edac_index,
 	memset(&pos, 0, sizeof(pos));
 	row = 0;
 	chn = 0;
-	debugf4("%s: initializing %d dimms\n", __func__, tot_dimms);
+	debugf4("%s: initializing %d %s\n", __func__, tot_dimms,
+		per_rank ? "ranks" : "dimms");
 	for (i = 0; i < tot_dimms; i++) {
 		chan = &csi[row].channels[chn];
 		dimm = GET_POS(lay, mci->dimms, n_layers,
 			       pos[0], pos[1], pos[2]);
 		dimm->mci = mci;
 
-		debugf2("%s: %d: dimm%zd (%d:%d:%d): row %d, chan %d\n", __func__,
-			i, (dimm - mci->dimms),
+		debugf2("%s: %d: %s%zd (%d:%d:%d): row %d, chan %d\n", __func__,
+			i, per_rank ? "rank" : "dimm", (dimm - mci->dimms),
 			pos[0], pos[1], pos[2], row, chn);
 
 		/*
@@ -1004,8 +1019,10 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type,
 			 * get csrow/channel of the dimm, in order to allow
 			 * incrementing the compat API counters
 			 */
-			debugf4("%s: dimm csrows (%d,%d)\n",
-				__func__, dimm->csrow, dimm->cschannel);
+			debugf4("%s: %s csrows map: (%d,%d)\n",
+				__func__,
+				mci->mem_is_per_rank ? "rank" : "dimm",
+				dimm->csrow, dimm->cschannel);
 			if (row == -1)
 				row = dimm->csrow;
 			else if (row >= 0 && row != dimm->csrow)
diff --git a/drivers/edac/edac_mc_sysfs.c b/drivers/edac/edac_mc_sysfs.c
index dd934c2..4452983 100644
--- a/drivers/edac/edac_mc_sysfs.c
+++ b/drivers/edac/edac_mc_sysfs.c
@@ -567,8 +567,7 @@ static struct kobj_type ktype_dimm = {
 };
 /* Create a CSROW object under specifed edac_mc_device */
 static int edac_create_dimm_object(struct mem_ctl_info *mci,
-					struct dimm_info *dimm, int index,
-					bool is_rank)
+					struct dimm_info *dimm, int index)
 {
 	struct kobject *kobj_mci = &mci->edac_mci_kobj;
 	struct kobject *kobj;
@@ -587,10 +586,10 @@ static int edac_create_dimm_object(struct mem_ctl_info *mci,
 	}
 
 	/* Instanstiate the dimm object */
-	if (!is_rank)
-		nodename = "dimm%d";
-	else
+	if (mci->mem_is_per_rank)
 		nodename = "rank%d";
+	else
+		nodename = "dimm%d";
 	err = kobject_init_and_add(&dimm->kobj, &ktype_dimm, kobj_mci,
 				nodename, index);
 	if (err)
@@ -1344,7 +1343,6 @@ int edac_create_sysfs_mci_device(struct mem_ctl_info *mci)
 	int err;
 	struct csrow_info *csrow;
 	struct kobject *kobj_mci = &mci->edac_mci_kobj;
-	bool is_rank = false;
 
 	debugf0("%s() idx=%d\n", __func__, mci->mc_idx);
 
@@ -1393,13 +1391,6 @@ int edac_create_sysfs_mci_device(struct mem_ctl_info *mci)
 		}
 	}
 
-	for (i = 0; i < mci->n_layers; i++) {
-		if (mci->layers[i].type == EDAC_MC_LAYER_CHIP_SELECT) {
-			is_rank = true;
-			break;
-		}
-	}
-
 	/*
 	 * Make directories for each DIMM object under the mc<id> kobject
 	 */
@@ -1420,7 +1411,7 @@ int edac_create_sysfs_mci_device(struct mem_ctl_info *mci)
 			printk(KERN_CONT "\n");
 		}
 #endif
-		err = edac_create_dimm_object(mci, dimm, j, is_rank);
+		err = edac_create_dimm_object(mci, dimm, j);
 		if (err) {
 			debugf1("%s() failure: create dimm %d obj\n",
 				__func__, j);
diff --git a/include/linux/edac.h b/include/linux/edac.h
index 895c4a8..e3f5324 100644
--- a/include/linux/edac.h
+++ b/include/linux/edac.h
@@ -605,9 +605,19 @@ struct mem_ctl_info {
 	struct csrow_info *csrows;
 	unsigned num_csrows, num_cschannel;
 
-	/* Memory Controller hierarchy */
+	/*
+	 * Memory Controller hierarchy
+	 *
+	 * There are basically two types of memory controller: the ones that
+	 * sees memory sticks ("dimms"), and the ones that sees memory ranks.
+	 * All old memory controllers enumerate memories per rank, but most
+	 * of the recent drivers enumerate memories per DIMM, instead.
+	 * When the memory controller is per rank, mem_is_per_rank is true.
+	 */
 	unsigned n_layers;
 	struct edac_mc_layer *layers;
+	bool mem_is_per_rank;
+
 	/*
 	 * DIMM info. Will eventually remove the entire csrows_info some day
 	 */
-- 
1.7.8

[PATCH 3/4] amd64_edac: Fix the rank number of pages count

[Mauro Carvalho Chehab]

Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
---
 drivers/edac/amd64_edac.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index ea7eb9a..d74bcd3 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -2227,7 +2227,7 @@ static int init_csrows(struct mem_ctl_info *mci)
 		for (j = 0; j < pvt->channel_count; j++) {
 			csrow->channels[j].dimm->mtype = mtype;
 			csrow->channels[j].dimm->edac_mode = edac_mode;
-			csrow->channels[j].dimm->nr_pages = nr_pages / pvt->channel_count;
+			csrow->channels[j].dimm->nr_pages = nr_pages;
 
 		}
 
-- 
1.7.8

[PATCH 4/4] i5100_edac: Fix a warning on a debug message

[Mauro Carvalho Chehab]

drivers/edac/i5100_edac.c: In function ‘i5100_init_csrows’:
drivers/edac/i5100_edac.c:864:3: warning: format ‘%d’ expects argument of type ‘int’, but argument 5 has type ‘long unsigned int’ [-Wformat]

Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
---
 drivers/edac/i5100_edac.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/edac/i5100_edac.c b/drivers/edac/i5100_edac.c
index 2eb44d8..254d7e4 100644
--- a/drivers/edac/i5100_edac.c
+++ b/drivers/edac/i5100_edac.c
@@ -861,7 +861,7 @@ static void __devinit i5100_init_csrows(struct mem_ctl_info *mci)
 			"DIMM%u",
 			i5100_rank_to_slot(mci, chan, rank));
 
-		debugf2("dimm channel %d, rank %d, size %d\n",
+		debugf2("dimm channel %d, rank %d, size %zd\n",
 			chan, rank, PAGES_TO_MiB(npages));
 	}
 }
-- 
1.7.8

Re: [PATCH 0/4] Some fixes over the last EDAC series

[Borislav Petkov]

On Mon, Mar 12, 2012 at 09:48:31AM -0300, Mauro Carvalho Chehab wrote:
> I may fold those patches when submitting my git tree to Linus, but
> it is better to keep them as incremental patches for the reviewers to
> not need to review the entire patch series again.

Yes, please do fold them into the series because no one has reviewed
the whole series anyway yet and besides, we're still discussing earlier
patches.

Thanks.

-- 
Regards/Gruss,
Boris.

Advanced Micro Devices GmbH
Einsteinring 24, 85609 Dornach
GM: Alberto Bozzo
Reg: Dornach, Landkreis Muenchen
HRB Nr. 43632 WEEE Registernr: 129 19551

Re: [PATCH 3/4] amd64_edac: Fix the rank number of pages count

[Borislav Petkov]

On Mon, Mar 12, 2012 at 09:48:34AM -0300, Mauro Carvalho Chehab wrote:
> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
> ---
>  drivers/edac/amd64_edac.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
> index ea7eb9a..d74bcd3 100644
> --- a/drivers/edac/amd64_edac.c
> +++ b/drivers/edac/amd64_edac.c
> @@ -2227,7 +2227,7 @@ static int init_csrows(struct mem_ctl_info *mci)
>  		for (j = 0; j < pvt->channel_count; j++) {
>  			csrow->channels[j].dimm->mtype = mtype;
>  			csrow->channels[j].dimm->edac_mode = edac_mode;
> -			csrow->channels[j].dimm->nr_pages = nr_pages / pvt->channel_count;
> +			csrow->channels[j].dimm->nr_pages = nr_pages;
>

This one has, again no commit message :( but nevertheless, I already
have a fix queued:

http://git.kernel.org/?p=linux/kernel/git/bp/bp.git;a=commitdiff;h=98c35aebc9734c1c970e3b4654dc8bd2e34f2a20

Thanks.

-- 
Regards/Gruss,
Boris.

Advanced Micro Devices GmbH
Einsteinring 24, 85609 Dornach
GM: Alberto Bozzo
Reg: Dornach, Landkreis Muenchen
HRB Nr. 43632 WEEE Registernr: 129 19551