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From: Felipe Balbi <balbi@ti.com>
To: Hiroshi Doyu <hdoyu@nvidia.com>
Cc: "balbi@ti.com" <balbi@ti.com>,
	"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
	"ccross@android.com" <ccross@android.com>,
	"olof@lixom.net" <olof@lixom.net>,
	"swarren@wwwdotorg.org" <swarren@wwwdotorg.org>,
	"linux@arm.linux.org.uk" <linux@arm.linux.org.uk>,
	"tony@atomide.com" <tony@atomide.com>,
	"hsweeten@visionengravers.com" <hsweeten@visionengravers.com>,
	"jamie@jamieiles.com" <jamie@jamieiles.com>,
	"rob.herring@calxeda.com" <rob.herring@calxeda.com>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 2/3] ARM: tegra: Add SMMU enabler in AHB
Date: Tue, 24 Apr 2012 15:41:18 +0300	[thread overview]
Message-ID: <20120424124115.GL8444@arwen.pp.htv.fi> (raw)
In-Reply-To: <20120424.153930.1438573079107186567.hdoyu@nvidia.com>

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On Tue, Apr 24, 2012 at 02:39:30PM +0200, Hiroshi Doyu wrote:
> From: Felipe Balbi <balbi@ti.com>
> Subject: Re: [PATCH v2 2/3] ARM: tegra: Add SMMU enabler in AHB
> Date: Tue, 24 Apr 2012 14:32:52 +0200
> Message-ID: <20120424123248.GG8444@arwen.pp.htv.fi>
> 
> > * PGP Signed by an unknown key
> > 
> > Hi,
> > 
> > On Tue, Apr 24, 2012 at 03:05:15PM +0300, Hiroshi DOYU wrote:
> > > @@ -95,6 +98,21 @@ static inline void gizmo_writel(unsigned long value, unsigned long offset)
> > >  	writel(value, tegra_ahb->regs + offset);
> > >  }
> > >  
> > > +#ifdef CONFIG_ARCH_TEGRA_3x_SOC
> > > +
> > > +void tegra_ahb_enable_smmu(void)
> > > +{
> > > +	unsigned long val;
> > > +
> > > +	val = gizmo_readl(AHB_ARBITRATION_XBAR_CTRL);
> > > +	val |= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE_DONE <<
> > > +		AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE_SHIFT;
> > > +	gizmo_writel(val, AHB_ARBITRATION_XBAR_CTRL);
> > > +}
> > > +EXPORT_SYMBOL(tegra_ahb_enable_smmu);
> > 
> > ok, so this is the only place where you need that global pointer. Who
> > would call this ? Can you do runtime detection of the SoC and enable
> > SMMU based on that ?
> > 
> > I mean, will this function always be called for TEGRA 3 SoCs or is there
> > another condition to that ?
> 
> Only Tegra3 has SMMU.

but all of them ? In that case, you could call this from probe itself,
right ? But an ifdef won't work in all cases, so you need to do runtime
detection based on some revision register or cpu detection...

-- 
balbi

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  reply	other threads:[~2012-04-24 12:42 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-04-24 12:05 [PATCH v2 1/3] ARM: tegra: Add AHB driver Hiroshi DOYU
2012-04-24 12:05 ` [PATCH v2 2/3] ARM: tegra: Add SMMU enabler in AHB Hiroshi DOYU
2012-04-24 12:32   ` Felipe Balbi
2012-04-24 12:39     ` Hiroshi Doyu
2012-04-24 12:41       ` Felipe Balbi [this message]
2012-04-24 13:03         ` Hiroshi Doyu
2012-04-24 13:25           ` Felipe Balbi
2012-04-24 19:59   ` Russell King - ARM Linux
2012-04-24 12:05 ` [PATCH v2 3/3] iommu/tegra: smmu: Refrain from accessing to AHB registers Hiroshi DOYU
2012-04-24 12:16 ` [PATCH v2 1/3] ARM: tegra: Add AHB driver Felipe Balbi
2012-04-24 19:49   ` Stephen Warren
2012-04-24 20:31     ` Felipe Balbi
2012-04-24 19:56 ` Russell King - ARM Linux
2012-04-25  5:37   ` Hiroshi Doyu
2012-04-25  7:46     ` Felipe Balbi
2012-04-25 12:15       ` Arnd Bergmann
2012-04-25 15:59         ` Stephen Warren
2012-04-26  5:49           ` Hiroshi Doyu
2012-04-26  8:14           ` Peter De Schrijver

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