[PATCH 2/3] gpio-sch: Add Intel Centerton DeviceID for GPIO

[PATCH 2/3] gpio-sch: Add Intel Centerton DeviceID for GPIO

[Seth Heasley]

This patch adds the Intel Centerton processor DeviceID for GPIO. The DeviceID is defined in include/linux/pci_ids.h

Signed-off-by: Seth Heasley <seth.heasley@intel.com>
---
 drivers/gpio/Kconfig    |    9 ++++++---
 drivers/gpio/gpio-sch.c |    8 ++++++++
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index e03653d..d84eb4d 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -162,13 +162,13 @@ config GPIO_VR41XX
 	  Say yes here to support the NEC VR4100 series General-purpose I/O Uint
 
 config GPIO_SCH
-	tristate "Intel SCH/TunnelCreek GPIO"
+	tristate "Intel SCH/TunnelCreek/Centerton GPIO"
 	depends on PCI && X86
 	select MFD_CORE
 	select LPC_SCH
 	help
-	  Say yes here to support GPIO interface on Intel Poulsbo SCH
-	  or Intel Tunnel Creek processor.
+	  Say yes here to support GPIO interface on Intel Poulsbo SCH,
+	  Intel Tunnel Creek processor or Intel Centerton processor.
 	  The Intel SCH contains a total of 14 GPIO pins. Ten GPIOs are
 	  powered by the core power rail and are turned off during sleep
 	  modes (S3 and higher). The remaining four GPIOs are powered by
@@ -177,6 +177,9 @@ config GPIO_SCH
 	  system from the Suspend-to-RAM state.
 	  The Intel Tunnel Creek processor has 5 GPIOs powered by the
 	  core power rail and 9 from suspend power supply.
+	  The Intel Centerton processor has a total of 30 GPIO pins.
+	  Twenty-one are powered by the core power rail and 9 from the
+	  suspend power supply.
 
 config GPIO_VX855
 	tristate "VIA VX855/VX875 GPIO"
diff --git a/drivers/gpio/gpio-sch.c b/drivers/gpio/gpio-sch.c
index 8cadf4d..424dce8 100644
--- a/drivers/gpio/gpio-sch.c
+++ b/drivers/gpio/gpio-sch.c
@@ -232,6 +232,14 @@ static int __devinit sch_gpio_probe(struct platform_device *pdev)
 			sch_gpio_resume.ngpio = 9;
 			break;
 
+		case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
+			sch_gpio_core.base = 0;
+			sch_gpio_core.ngpio = 21;
+
+			sch_gpio_resume.base = 21;
+			sch_gpio_resume.ngpio = 9;
+			break;
+
 		default:
 			return -ENODEV;
 	}
-- 
1.7.4.4

Re: [PATCH 2/3] gpio-sch: Add Intel Centerton DeviceID for GPIO

[Linus Walleij]

On Tue, Apr 17, 2012 at 11:04 PM, Seth Heasley <seth.heasley@intel.com> wrote:

> This patch adds the Intel Centerton processor DeviceID for GPIO. The DeviceID is defined in include/linux/pci_ids.h
>
> Signed-off-by: Seth Heasley <seth.heasley@intel.com>

That's straight-forward :)

Acked-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

Re: [PATCH 2/3] gpio-sch: Add Intel Centerton DeviceID for GPIO

[Grant Likely]

On Wed, 18 Apr 2012 13:42:26 +0200, Linus Walleij <linus.walleij@linaro.org> wrote:
> On Tue, Apr 17, 2012 at 11:04 PM, Seth Heasley <seth.heasley@intel.com> wrote:
> 
> > This patch adds the Intel Centerton processor DeviceID for GPIO. The DeviceID is defined in include/linux/pci_ids.h
> >
> > Signed-off-by: Seth Heasley <seth.heasley@intel.com>
> 
> That's straight-forward :)
> 
> Acked-by: Linus Walleij <linus.walleij@linaro.org>

Applied, thanks.

g.

> 
> Yours,
> Linus Walleij

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies, Ltd.

Re: [PATCH 2/3] gpio-sch: Add Intel Centerton DeviceID for GPIO

[Grant Likely]

On Thu, May 17, 2012 at 5:34 PM, Grant Likely <grant.likely@secretlab.ca> wrote:
> On Wed, 18 Apr 2012 13:42:26 +0200, Linus Walleij <linus.walleij@linaro.org> wrote:
>> On Tue, Apr 17, 2012 at 11:04 PM, Seth Heasley <seth.heasley@intel.com> wrote:
>>
>> > This patch adds the Intel Centerton processor DeviceID for GPIO. The DeviceID is defined in include/linux/pci_ids.h
>> >
>> > Signed-off-by: Seth Heasley <seth.heasley@intel.com>
>>
>> That's straight-forward :)
>>
>> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>
> Applied, thanks.

Oops, this depends on the pci device id change in patch 1 which Samuel
is picking up.  I'm dropping it from my tree since it should get
merged with the other patches.

g.