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From: Andi Kleen <ak@linux.intel.com>
To: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Andi Kleen <andi@firstfloor.org>,
	linux-kernel@vger.kernel.org, eranian@google.com
Subject: Re: [PATCH 1/5] perf, x86: Don't assume the alternative cycles encoding is architectural
Date: Wed, 6 Jun 2012 07:49:52 -0700	[thread overview]
Message-ID: <20120606144952.GK28225@tassilo.jf.intel.com> (raw)
In-Reply-To: <1338993726.2749.125.camel@twins>

On Wed, Jun 06, 2012 at 04:42:06PM +0200, Peter Zijlstra wrote:
> On Wed, 2012-06-06 at 07:35 -0700, Andi Kleen wrote:
> > > But simply disabling it for a model isn't how you do things. 
> > 
> > Do you want it enabled per model?  I can turn the flag around.
> > Anything else? 
> 
> The below is a refresh from a patch I did about a year ago when we ran
> into the SNB trainwreck. I never merged it because SNB.. but IVB seems
> to work.

Hmm, your line numbers do not fully match mine

Is this for the intel_pmu or for the core_pmu?

> +     .pebs_aliases           = intel_pebs_aliases_core2,

In any case since the code later does

        version = eax.split.version_id;
        if (version < 2)
                x86_pmu = core_pmu;
        else
                x86_pmu = intel_pmu;

so core_pmu would be active even without model check, which would
be still wrong.

So your patch would fix the problem iff you only fill in the pebs_aliases
in the model number switch for known Core model numbers.

If you fix that it would be a valid replacement for mine I believe.

-Andi

  reply	other threads:[~2012-06-06 14:49 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-06-06  0:56 [PATCH 1/5] perf, x86: Don't assume the alternative cycles encoding is architectural Andi Kleen
2012-06-06  0:56 ` [PATCH 2/5] perf, x86: Don't assume there can be only 4 PEBS events Andi Kleen
2012-06-06 15:00   ` Peter Zijlstra
2012-06-06 16:10     ` Andi Kleen
2012-06-06 17:25       ` Peter Zijlstra
2012-06-06 16:17   ` [tip:perf/core] perf/x86: Don' t " tip-bot for Andi Kleen
2012-06-06  0:56 ` [PATCH 3/5] perf, x86: Check LBR format capability Andi Kleen
2012-06-06  4:29   ` Andi Kleen
2012-06-06 10:40   ` Peter Zijlstra
2012-06-06 14:14     ` Andi Kleen
2012-06-06 14:22       ` Peter Zijlstra
2012-06-06 14:37         ` Andi Kleen
2012-06-06  0:56 ` [PATCH 4/5] x86: Add rdpmcl() Andi Kleen
2012-06-06 16:16   ` [tip:perf/core] " tip-bot for Andi Kleen
2012-06-06  0:56 ` [PATCH 5/5] perf, x86: Prefer RDPMC over RDMSR for reading counters Andi Kleen
2012-06-06 10:46   ` Peter Zijlstra
2012-06-06 14:16     ` Andi Kleen
2012-06-06 14:21       ` Peter Zijlstra
2012-06-06 14:33         ` Stephane Eranian
2012-06-06 14:38           ` Peter Zijlstra
2012-06-06 14:41         ` Andi Kleen
2012-06-06 14:45           ` Peter Zijlstra
2012-06-06 10:39 ` [PATCH 1/5] perf, x86: Don't assume the alternative cycles encoding is architectural Peter Zijlstra
2012-06-06 14:12   ` Andi Kleen
2012-06-06 14:14     ` Peter Zijlstra
2012-06-06 14:23       ` Andi Kleen
2012-06-06 14:28         ` Peter Zijlstra
2012-06-06 14:35           ` Andi Kleen
2012-06-06 14:42             ` Peter Zijlstra
2012-06-06 14:49               ` Andi Kleen [this message]
2012-06-06 14:53                 ` Peter Zijlstra
2012-06-06 16:08                   ` Andi Kleen
2012-06-06 17:10                     ` Peter Zijlstra
2012-06-06 17:48                       ` Andi Kleen

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