From: Andi Kleen <andi@firstfloor.org>
To: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Andi Kleen <andi@firstfloor.org>,
linux-kernel@vger.kernel.org, eranian@google.com,
Andi Kleen <ak@linux.intel.com>
Subject: Re: [PATCH 2/5] perf, x86: Don't assume there can be only 4 PEBS events
Date: Wed, 6 Jun 2012 18:10:44 +0200 [thread overview]
Message-ID: <20120606161044.GH27374@one.firstfloor.org> (raw)
In-Reply-To: <1338994803.2749.132.camel@twins>
On Wed, Jun 06, 2012 at 05:00:03PM +0200, Peter Zijlstra wrote:
> On Tue, 2012-06-05 at 17:56 -0700, Andi Kleen wrote:
> > On Sandy Bridge in non HT mode there are 8 counters available. Since every
> > counter can write a PEBS record assuming there are 4 max is incorrect. Use
> > the reported counter number -- with an upper limit for a static array -- instead.
>
>
> While I queued this patch, its effectively a NOP since all SNB PEBS
> constraints are still on 4 counters.
Yes need to update the constraints too. I think Stephane was looking at that.
Perhaps two sets depending on the counters in CPUID?
FWIW I saw the warn on triggering.
-Andi
--
ak@linux.intel.com -- Speaking for myself only.
next prev parent reply other threads:[~2012-06-06 16:10 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-06 0:56 [PATCH 1/5] perf, x86: Don't assume the alternative cycles encoding is architectural Andi Kleen
2012-06-06 0:56 ` [PATCH 2/5] perf, x86: Don't assume there can be only 4 PEBS events Andi Kleen
2012-06-06 15:00 ` Peter Zijlstra
2012-06-06 16:10 ` Andi Kleen [this message]
2012-06-06 17:25 ` Peter Zijlstra
2012-06-06 16:17 ` [tip:perf/core] perf/x86: Don' t " tip-bot for Andi Kleen
2012-06-06 0:56 ` [PATCH 3/5] perf, x86: Check LBR format capability Andi Kleen
2012-06-06 4:29 ` Andi Kleen
2012-06-06 10:40 ` Peter Zijlstra
2012-06-06 14:14 ` Andi Kleen
2012-06-06 14:22 ` Peter Zijlstra
2012-06-06 14:37 ` Andi Kleen
2012-06-06 0:56 ` [PATCH 4/5] x86: Add rdpmcl() Andi Kleen
2012-06-06 16:16 ` [tip:perf/core] " tip-bot for Andi Kleen
2012-06-06 0:56 ` [PATCH 5/5] perf, x86: Prefer RDPMC over RDMSR for reading counters Andi Kleen
2012-06-06 10:46 ` Peter Zijlstra
2012-06-06 14:16 ` Andi Kleen
2012-06-06 14:21 ` Peter Zijlstra
2012-06-06 14:33 ` Stephane Eranian
2012-06-06 14:38 ` Peter Zijlstra
2012-06-06 14:41 ` Andi Kleen
2012-06-06 14:45 ` Peter Zijlstra
2012-06-06 10:39 ` [PATCH 1/5] perf, x86: Don't assume the alternative cycles encoding is architectural Peter Zijlstra
2012-06-06 14:12 ` Andi Kleen
2012-06-06 14:14 ` Peter Zijlstra
2012-06-06 14:23 ` Andi Kleen
2012-06-06 14:28 ` Peter Zijlstra
2012-06-06 14:35 ` Andi Kleen
2012-06-06 14:42 ` Peter Zijlstra
2012-06-06 14:49 ` Andi Kleen
2012-06-06 14:53 ` Peter Zijlstra
2012-06-06 16:08 ` Andi Kleen
2012-06-06 17:10 ` Peter Zijlstra
2012-06-06 17:48 ` Andi Kleen
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