Re: [PATCH 1/5] perf, x86: Improve basic Ivy Bridge support v3

Peter Zijlstra
2012-07-02T20:18:34Z

On Mon, 2012-07-02 at 21:58 +0200, Andi Kleen wrote:
> On Mon, Jul 02, 2012 at 09:26:34PM +0200, Peter Zijlstra wrote:
> > On Mon, 2012-07-02 at 11:43 -0700, Andi Kleen wrote:
> > > - As Stephane pointed out .code=0xb1, .umask=0x01 is gone from the
> > > event list,
> > > so don't do a generic backend stall event on IvyBridge.
> >
> > 325462-043US, May 2012:
> >
> > Page 3135, Table 19-2. Non-Architectural Performance Events In the
> > Processor Core of Third Generation Intel Core i7, i5, i3 Processors
>
> The table is outdated.
>
> But if you insist can readd it. It's just unlikely to work.

But you didn't state anything of the like. If anybody deviates from the
SDM they had better well bloody mention it. And you being from Intel, I
would very much like to have an Official (TM) statement right along with
it. Preferably in the form of a new SDM.

Also, you didn't CC Stephane, nor was it mentioned where this
observation was made from.

In short, the typical shoddy quality one expects from you.