From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760569Ab2ILRrM (ORCPT ); Wed, 12 Sep 2012 13:47:12 -0400 Received: from co1ehsobe004.messaging.microsoft.com ([216.32.180.187]:47161 "EHLO co1outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752804Ab2ILRrI (ORCPT ); Wed, 12 Sep 2012 13:47:08 -0400 X-Forefront-Antispam-Report: CIP:163.181.249.108;KIP:(null);UIP:(null);IPV:NLI;H:ausb3twp01.amd.com;RD:none;EFVD:NLI X-SpamScore: -2 X-BigFish: VPS-2(zz98dI1432Izz1202h1d1ah1d2ahzz8275bh8275dhz2dh668h839h944hd25hf0ah11b5h121eh1220h1288h12a5h12a9h12bdh1155h) X-WSS-ID: 0MA902D-01-FME-02 X-M-MSG: Date: Wed, 12 Sep 2012 19:46:55 +0200 From: Robert Richter To: David Ahern CC: , , , Ingo Molnar , Gleb Natapov , Avi Kivity Subject: Re: [PATCH 1/3] perf tool: precise mode requires exclude_guest Message-ID: <20120912174655.GA8285@erda.amd.com> References: <1347462990-29481-1-git-send-email-dsahern@gmail.com> <1347462990-29481-2-git-send-email-dsahern@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <1347462990-29481-2-git-send-email-dsahern@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginatorOrg: amd.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12.09.12 09:16:28, David Ahern wrote: > Summary of events per Peter: > > "Intel PEBS in VT-x context uses the DS address as a guest linear address, > even though its programmed by the host as a host linear address. This > either results in guest memory corruption and or the hardware faulting and > 'crashing' the virtual machine. Therefore we have to disable PEBS on VT-x > enter and re-enable on VT-x exit, enforcing a strict exclude_guest. > > AMB IBS does work but doesn't currently support exclude_* at all, > setting an exclude_* bit will make it fail." > > This patch handles userspace perf command, setting the exclude_guest > attribute if precise mode is requested, but only if a user has not > specified a request for guest or host only profiling (G or H attribute). > > Kernel side AMD currently ignores all exclude_* bits, so there is no impact > to existing IBS code paths. Robert Richter has a patch where IBS code will > return EINVAL if an exclude_* bit is set. When this goes in it means use > of :p on AMD with IBS will first fail with EINVAL (because exclude_guest > will be set). Then the existing fallback code within perf will unset > exclude_guest and try again. The second attempt will succeed if the CPU > supports IBS profiling. > > Signed-off-by: David Ahern > Cc: Ingo Molnar > Cc: Peter Zijlstra > Cc: Robert Richter > Cc: Gleb Natapov > Cc: Avi Kivity > Link: https://lkml.org/lkml/2012/7/9/264 > --- > tools/perf/util/parse-events.c | 3 +++ > 1 file changed, 3 insertions(+) Acked-by: Robert Richter I tested the patch set with AMD IBS and it works fine. -Robert > > diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c > index 44afcf4..696cc7e 100644 > --- a/tools/perf/util/parse-events.c > +++ b/tools/perf/util/parse-events.c > @@ -694,6 +694,9 @@ static int get_event_modifier(struct event_modifier *mod, char *str, > eH = 0; > } else if (*str == 'p') { > precise++; > + /* use of precise requires exclude_guest */ > + if (!exclude_GH) > + eG = 1; > } else > break; > > -- > 1.7.10.1 > > -- Advanced Micro Devices, Inc. Operating System Research Center