From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757546Ab2IZRRA (ORCPT ); Wed, 26 Sep 2012 13:17:00 -0400 Received: from mail.skyhub.de ([78.46.96.112]:46628 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756921Ab2IZRQ7 (ORCPT ); Wed, 26 Sep 2012 13:16:59 -0400 Date: Wed, 26 Sep 2012 19:17:22 +0200 From: Borislav Petkov To: Mike Galbraith Cc: Linus Torvalds , Peter Zijlstra , Mel Gorman , Nikolay Ulyanitsky , linux-kernel@vger.kernel.org, Andreas Herrmann , Andrew Morton , Thomas Gleixner , Ingo Molnar , Suresh Siddha Subject: Re: 20% performance drop on PostgreSQL 9.2 from kernel 3.5.3 to 3.6-rc5 on AMD chipsets - bisected Message-ID: <20120926171721.GC5339@x1.osrc.amd.com> Mail-Followup-To: Borislav Petkov , Mike Galbraith , Linus Torvalds , Peter Zijlstra , Mel Gorman , Nikolay Ulyanitsky , linux-kernel@vger.kernel.org, Andreas Herrmann , Andrew Morton , Thomas Gleixner , Ingo Molnar , Suresh Siddha References: <20120924192056.GB4082@liondog.tnic> <1348538258.7100.23.camel@marge.simpson.net> <1348574286.3881.40.camel@twins> <20120925131736.GA30652@x1.osrc.amd.com> <20120925170058.GC30158@x1.osrc.amd.com> <20120925184245.GA13694@liondog.tnic> <1348626206.7100.166.camel@marge.simpson.net> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1348626206.7100.166.camel@marge.simpson.net> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Sep 26, 2012 at 04:23:26AM +0200, Mike Galbraith wrote: > On Tue, 2012-09-25 at 20:42 +0200, Borislav Petkov wrote: > > > Right, so why did we need it all, in the first place? There has to be > > some reason for it. > > Easy. Take two communicating tasks. Is an affine wakeup a good idea? > It depends on how much execution overlap there is. Wake affine when > there is overlap larger than cache miss cost, and you just tossed > throughput into the bin. > > select_idle_sibling() was originally about shared L2, where any overlap > was salvageable. On modern processors with no shared L2, Oh, but we do have shared L2s in the Bulldozer uarch (a subset of the modern AMD processors :)). > you have to get past the cost, but the gain is still there. Intel > wins with loads that AMD loses very bady on, so I can only guess that > Intel must feed caches more efficiently. Dunno. It just doesn't matter > though, point is that there is a win to be had in both cases, the > breakeven just isn't at the same point. Well, I guess selecting the proper core in the hierarchy depending on the workload is one of those hard problems. Teaching select_idle_sibling to detect the breakeven point and act accordingly would be not that easy then... Thanks. -- Regards/Gruss, Boris.