From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751032Ab2I2ULP (ORCPT ); Sat, 29 Sep 2012 16:11:15 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:43542 "EHLO out1-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750810Ab2I2ULM (ORCPT ); Sat, 29 Sep 2012 16:11:12 -0400 X-Sasl-enc: rhlTgP2Or+A5vqwo+Syl/JmQX0SCps0nL26w+gzJvhAy 1348949471 Date: Sat, 29 Sep 2012 17:11:07 -0300 From: Henrique de Moraes Holschuh To: "H. Peter Anvin" Cc: Peter Hurley , "zhenzhong.duan@oracle.com" , Thomas Gleixner , Ingo Molnar , "x86@kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [RFC] x86: mtrr: Constrain WB MTRR to max phys mem prior to cleanup Message-ID: <20120929201107.GB8329@khazad-dum.debian.net> References: <1347039854.6288.8.camel@thor> <504A3FA9.1050502@zytor.com> <504D6490.2060606@oracle.com> <1348853876.2229.22.camel@thor> <5066680E.3090907@zytor.com> <20120929104611.GB14974@khazad-dum.debian.net> <30701c46-a57e-49f2-9273-6f725c8463e0@email.android.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <30701c46-a57e-49f2-9273-6f725c8463e0@email.android.com> X-GPG-Fingerprint: 1024D/1CDB0FE3 5422 5C61 F6B7 06FB 7E04 3738 EE25 DE3F 1CDB 0FE3 User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, 29 Sep 2012, H. Peter Anvin wrote: > PAT support are lacking only in the Pentium Pro and Pentium II. Sorry, if > you're using crap that old, you don't get to screw up the kernel for > everyone else. PAT is blacklisted for x86_model < 15 on Intel, which covers a lot more boxes than p-pro and pII. There is a comment on kernel/cpu/intel.c: /* * There is a known erratum on Pentium III and Core Solo * and Core Duo CPUs. * " Page with PAT set to WC while associated MTRR is UC * may consolidate to UC " * Because of this erratum, it is better to stick with * setting WC in MTRR rather than using PAT on these CPUs. * * Enable PAT WC only on P4, Core 2 or later CPUs. */ if (c->x86 == 6 && c->x86_model < 15) clear_cpu_cap(c, X86_FEATURE_PAT); Intel doesn't make it easy to get all processor specification updates at once so that I could hunt down every processor which acknowledges the existence of that errata before replying, so I will assume for the moment that the comment is mostly correct. -- "One disk to rule them all, One disk to find them. One disk to bring them all and in the darkness grind them. In the Land of Redmond where the shadows lie." -- The Silicon Valley Tarot Henrique Holschuh