From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751805Ab2LSXAC (ORCPT ); Wed, 19 Dec 2012 18:00:02 -0500 Received: from tx2ehsobe005.messaging.microsoft.com ([65.55.88.15]:51865 "EHLO tx2outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751004Ab2LSW7y (ORCPT ); Wed, 19 Dec 2012 17:59:54 -0500 X-Forefront-Antispam-Report: CIP:163.181.249.109;KIP:(null);UIP:(null);IPV:NLI;H:ausb3twp02.amd.com;RD:none;EFVD:NLI X-SpamScore: 1 X-BigFish: VPS1(zz98dI1432Izz1de0h1202h1e76h1d1ah1d2ahz70kzz2dh668h839h944hd25hd2bhf0ah1220h1288h12a5h12a9h12bdh137ah13b6h1441h1504h1537h153bh162dh1631h1758h1155h) X-WSS-ID: 0MFAVVG-02-1EW-02 X-M-MSG: Date: Wed, 19 Dec 2012 16:59:41 -0600 From: Jacob Shin To: Borislav Petkov , "H. Peter Anvin" , Yinghai Lu , "H. Peter Anvin" , "Yu, Fenghua" , "mingo@kernel.org" , "linux-kernel@vger.kernel.org" , "tglx@linutronix.de" , "linux-tip-commits@vger.kernel.org" , Konrad Rzeszutek Wilk , Stefano Stabellini Subject: Re: [tip:x86/microcode] x86/microcode_intel_early.c: Early update ucode on Intel's CPU Message-ID: <20121219225941.GB2968@jshin-Toonie> References: <50CCEE49.3080801@zytor.com> <50CCF6F6.4020107@zytor.com> <50CD04F1.8020902@zytor.com> <0dcbce7a-d2ae-44fa-9658-81590f71ec47@email.android.com> <20121219220504.GA32212@jshin-Toonie> <50D23EE8.7030904@zytor.com> <20121219225155.GK24895@liondog.tnic> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20121219225155.GK24895@liondog.tnic> User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginatorOrg: amd.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Dec 19, 2012 at 11:51:55PM +0100, Borislav Petkov wrote: > On Wed, Dec 19, 2012 at 02:25:44PM -0800, H. Peter Anvin wrote: > > The real question is what we can do to mitigate the damage. > > Let's try the first thing that comes to mind: waste a variable MTRR on > it: > > [ 0.000000] MTRR variable ranges enabled: > [ 0.000000] 0 base 000000000000 mask FFFF80000000 write-back > [ 0.000000] 1 base 000080000000 mask FFFFC0000000 write-back > [ 0.000000] 2 base 0000C0000000 mask FFFFF0000000 write-back > [ 0.000000] 3 base 000100000000 mask FFFF00000000 write-back > [ 0.000000] 4 base 000200000000 mask FFFFE0000000 write-back > [ 0.000000] 5 base 000220000000 mask FFFFF0000000 write-back > [ 0.000000] 6 disabled > [ 0.000000] 7 disabled > > one of those last two. This is a small box though so I'm guessing on 1T > boxes those last two won't be disabled. Jacob? I can check but right, they might be used up. But even if we had slots available, the memory range that needs to be covered is in large enough address and aligned in such a way that you cannot cover it with variable range MTRRs. > > -- > Regards/Gruss, > Boris. > > Sent from a fat crate under my desk. Formatting is fine. > -- >