From: Vinod Koul <vinod.koul@intel.com>
To: Andy Shevchenko <andriy.shevchenko@linux.jf.intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.jf.intel.com>,
Viresh Kumar <viresh.linux@gmail.com>,
linux-kernel@vger.kernel.org,
spear-devel <spear-devel@list.st.com>
Subject: Re: [PATCH 2/2] dw_dmac: return proper residue value
Date: Mon, 21 Jan 2013 06:22:05 -0800 [thread overview]
Message-ID: <20130121142205.GB26562@intel.com> (raw)
In-Reply-To: <1358761551.12502.39.camel@smile>
On Mon, Jan 21, 2013 at 11:45:51AM +0200, Andy Shevchenko wrote:
> > > + return 0;
> > hmmm, why not use BLOCK_TS value. That way you dont need to look at direction
> > and along with burst can easily calculate residue...
>
> Do you mean to read CTL hi/lo and do
>
> desc->len - ctlhi.block_ts * ctllo.src_tr_width?
>
Yes
> I think it could be not precise when memory-to-peripheral transfer is
> going on. In that case you probably will have src_tr_width like 32 bits,
> meanwhile peripheral may receive only byte stream.
Nope that is not the case.
SAR/DAR is always incremented in src/dstn_tr_width granularity. For example if
you are using MEM to DMA, then SAR will always increment in case of x86 in 4byte
granularity as we will read bursts not singles.
Also if check the spec, it says "Once the transfer starts, the read-back value is the
total number of data items already read from the source peripheral, regardless of
what is the flow controller"
So basically you get what is read from buffer in case of MEM->PER and get what
is read from FIFO in case of PER->MEM which IMO gives you better or equal results
than your calulation.
--
~Vinod
next prev parent reply other threads:[~2013-01-21 14:47 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-01-21 9:00 [PATCH 1/2] dw_dmac: fill len field of the descriptor Andy Shevchenko
2013-01-21 9:00 ` [PATCH 2/2] dw_dmac: return proper residue value Andy Shevchenko
2013-01-21 8:49 ` Vinod Koul
2013-01-21 9:45 ` Andy Shevchenko
2013-01-21 14:22 ` Vinod Koul [this message]
2013-01-22 7:24 ` Andy Shevchenko
2013-01-22 8:11 ` Viresh Kumar
2013-01-22 9:22 ` Andy Shevchenko
2013-01-22 9:40 ` Viresh Kumar
2013-01-23 9:12 ` Andy Shevchenko
2013-01-23 9:22 ` Viresh Kumar
2013-01-23 9:36 ` Andy Shevchenko
2013-01-23 9:51 ` Viresh Kumar
2013-01-23 10:20 ` Andy Shevchenko
2013-01-23 10:24 ` Viresh Kumar
2013-01-23 10:33 ` Andy Shevchenko
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