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Date: Tue, 12 Feb 2013 09:43:46 +0100
From: Ingo Molnar <mingo@kernel.org>
To: Andi Kleen <andi@firstfloor.org>
Cc: linux-kernel@vger.kernel.org, eranian@google.com,
        Andi Kleen <ak@linux.intel.com>
Subject: Re: [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler
 after the counter registers are reset
Message-ID: <20130212084346.GB19475@gmail.com>
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* Andi Kleen <andi@firstfloor.org> wrote:

> From: Andi Kleen <ak@linux.intel.com>
> 
> This avoids some problems with spurious PMIs on Haswell.
> Haswell seems to behave more like P4 in this regard. Do
> the same thing as the P4 perf handler by unmasking
> the NMI only at the end. Shouldn't make any difference
> for earlier non P4 cores.

Was this stress-tested on all affected main CPU types, or only 
on Haswell?

Thanks,

	Ingo