From: Ingo Molnar <mingo@kernel.org>
To: Andi Kleen <andi@firstfloor.org>
Cc: linux-kernel@vger.kernel.org, eranian@google.com,
Andi Kleen <ak@linux.intel.com>,
Peter Zijlstra <a.p.zijlstra@chello.nl>,
Arnaldo Carvalho de Melo <acme@infradead.org>
Subject: Re: [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset
Date: Wed, 13 Feb 2013 10:10:22 +0100 [thread overview]
Message-ID: <20130213091022.GB7630@gmail.com> (raw)
In-Reply-To: <20130212151426.GA30577@one.firstfloor.org>
* Andi Kleen <andi@firstfloor.org> wrote:
> On Tue, Feb 12, 2013 at 09:43:46AM +0100, Ingo Molnar wrote:
> > Was this stress-tested on all affected main CPU types, or only
> > on Haswell?
>
> I tested it on Haswell and Ivy Bridge. I can also try Westmere
> and a Saltwell(Atom), but for the majority of other family 6
> systems I'll need to rely on the community.
The systems you tested should be OK.
> White listing is somewhat difficult because it affects the
> architectural mode too.
Yeah, I'd rather avoid that.
> I don't really expect problems from this change, we should
> probably have always done it like this.
I expect potential problems: the ordering of the operations in
the NMI handler was always very fragile, resulting in hard to
debug hangs - which sometimes needed hours long very intense PMU
stress-testing to trigger.
That is why I asked how heavily you've tested this. Once the
series passes review I'll keep this patch last to make it easy
to revert/zap if it causes problems.
Thanks,
Ingo
next prev parent reply other threads:[~2013-02-13 9:10 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-02-07 19:23 Basic perf PMU support for Haswell v5 Andi Kleen
2013-02-07 19:23 ` [PATCH 1/5] perf, x86: Add PEBSv2 record support v2 Andi Kleen
2013-02-12 9:02 ` Ingo Molnar
2013-02-07 19:23 ` [PATCH 2/5] perf, x86: Basic Haswell PMU support v4 Andi Kleen
2013-02-07 19:23 ` [PATCH 3/5] perf, x86: Basic Haswell PEBS " Andi Kleen
2013-02-07 19:23 ` [PATCH 4/5] perf, x86: Support full width counting v2 Andi Kleen
2013-02-12 8:42 ` Ingo Molnar
2013-02-07 19:23 ` [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset Andi Kleen
2013-02-12 8:43 ` Ingo Molnar
2013-02-12 15:14 ` Andi Kleen
2013-02-13 9:10 ` Ingo Molnar [this message]
-- strict thread matches above, loose matches on Subject: below --
2013-02-18 18:48 Basic perf PMU support for Haswell v8 Andi Kleen
2013-02-18 18:48 ` [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset Andi Kleen
2013-02-13 16:08 Basic perf PMU support for Haswell v7 Andi Kleen
2013-02-13 16:08 ` [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset Andi Kleen
2013-02-12 22:04 Basic perf PMU support for Haswell v6 Andi Kleen
2013-02-12 22:04 ` [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset Andi Kleen
2013-02-05 1:49 Basic perf PMU support for Haswell v4 Andi Kleen
2013-02-05 1:49 ` [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset Andi Kleen
2013-02-02 1:54 Basic perf PMU support for Haswell v3 Andi Kleen
2013-02-02 1:54 ` [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset Andi Kleen
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