[PATCH] perf, x86: add Intel IvyBridge event scheduling constraints

[PATCH] perf, x86: add Intel IvyBridge event scheduling constraints

[Stephane Eranian]

Intel IvyBridge processor has different constraints compared
to SandyBridge. Therefore it needs its own contraint table.
This patch adds the constraint table. Without this patch,
the events listed in the patch may not be scheduled correctly
and bogus counts may be collected.

Signed-off-by: Stephane Eranian <eranian@google.com>
---
 arch/x86/kernel/cpu/perf_event_intel.c |   23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 4914e94..529c893 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -107,6 +107,27 @@ static struct event_constraint intel_snb_event_constraints[] __read_mostly =
 	EVENT_CONSTRAINT_END
 };
 
+static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
+{
+	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
+	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
+	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
+	INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
+	INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
+	INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
+	INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
+	INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
+	INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
+	INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
+	INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
+	INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
+	INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
+	INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
+	INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
+	INTEL_EVENT_CONSTRAINT(0xd3, 0xf), /*  MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
+	EVENT_CONSTRAINT_END
+};
+
 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
 {
 	INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
@@ -2095,7 +2116,7 @@ __init int intel_pmu_init(void)
 
 		intel_pmu_lbr_init_snb();
 
-		x86_pmu.event_constraints = intel_snb_event_constraints;
+		x86_pmu.event_constraints = intel_ivb_event_constraints;
 		x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
 		x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
 		x86_pmu.extra_regs = intel_snb_extra_regs;
-- 
1.7.9.5

[tip:perf/urgent] perf/x86: Add Intel IvyBridge event scheduling constraints

[tip-bot for Stephane Eranian]

Commit-ID:  69943182bb9e19e4b60ea5033f683ec1af1703a9
Gitweb:     http://git.kernel.org/tip/69943182bb9e19e4b60ea5033f683ec1af1703a9
Author:     Stephane Eranian <eranian@google.com>
AuthorDate: Wed, 20 Feb 2013 11:15:12 +0100
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Wed, 20 Feb 2013 11:22:46 +0100

perf/x86: Add Intel IvyBridge event scheduling constraints

Intel IvyBridge processor has different constraints compared
to SandyBridge. Therefore it needs its own contraint table.
This patch adds the constraint table.

Without this patch, the events listed in the patch may not be
scheduled correctly and bogus counts may be collected.

Signed-off-by: Stephane Eranian <eranian@google.com>
Cc: peterz@infradead.org
Cc: ak@linux.intel.com
Cc: acme@redhat.com
Cc: jolsa@redhat.com
Cc: namhyung.kim@lge.com
Link: http://lkml.kernel.org/r/1361355312-3323-1-git-send-email-eranian@google.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/kernel/cpu/perf_event_intel.c | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 4914e94..529c893 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -107,6 +107,27 @@ static struct event_constraint intel_snb_event_constraints[] __read_mostly =
 	EVENT_CONSTRAINT_END
 };
 
+static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
+{
+	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
+	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
+	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
+	INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
+	INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
+	INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
+	INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
+	INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
+	INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
+	INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
+	INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
+	INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
+	INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
+	INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
+	INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
+	INTEL_EVENT_CONSTRAINT(0xd3, 0xf), /*  MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
+	EVENT_CONSTRAINT_END
+};
+
 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
 {
 	INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
@@ -2095,7 +2116,7 @@ __init int intel_pmu_init(void)
 
 		intel_pmu_lbr_init_snb();
 
-		x86_pmu.event_constraints = intel_snb_event_constraints;
+		x86_pmu.event_constraints = intel_ivb_event_constraints;
 		x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
 		x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
 		x86_pmu.extra_regs = intel_snb_extra_regs;

Re: [PATCH] perf, x86: add Intel IvyBridge event scheduling constraints

[Andi Kleen]

On Wed, Feb 20, 2013 at 11:15:12AM +0100, Stephane Eranian wrote:
> Intel IvyBridge processor has different constraints compared
> to SandyBridge. Therefore it needs its own contraint table.
> This patch adds the constraint table. Without this patch,
> the events listed in the patch may not be scheduled correctly
> and bogus counts may be collected.

Thanks. I ran into this problem too and was about to write 
a similar patch.

> +	INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
> +	INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
> +	INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
> +	INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
> +	INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */


Except for LDM_PENDING the CYCLE_ACTIVITY events have been also added to Sandy Bridge.
So it should be also added there.

In fact I think you can still share the table because it would just add some 
non existent events to Sandy Bridge, which is a noop.

-Andi

Re: [PATCH] perf, x86: add Intel IvyBridge event scheduling constraints

[Stephane Eranian]

On Wed, Feb 20, 2013 at 4:43 PM, Andi Kleen <ak@linux.intel.com> wrote:
> On Wed, Feb 20, 2013 at 11:15:12AM +0100, Stephane Eranian wrote:
>> Intel IvyBridge processor has different constraints compared
>> to SandyBridge. Therefore it needs its own contraint table.
>> This patch adds the constraint table. Without this patch,
>> the events listed in the patch may not be scheduled correctly
>> and bogus counts may be collected.
>
> Thanks. I ran into this problem too and was about to write
> a similar patch.
>
>> +     INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
>> +     INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
>> +     INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
>> +     INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
>> +     INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
>
>
> Except for LDM_PENDING the CYCLE_ACTIVITY events have been also added to Sandy Bridge.
> So it should be also added there.
>
As far as I know and I double-checked the documentation I have, there
is no CYCLE_ACTIVITY
event on SNB or SNB-EP.

> In fact I think you can still share the table because it would just add some
> non existent events to Sandy Bridge, which is a noop.
>
I don't see the point of this, except saving a few bytes. Isn't it
better to keep each PMU separate?


> -Andi
>

Re: [PATCH] perf, x86: add Intel IvyBridge event scheduling constraints

[Andi Kleen]

> > Except for LDM_PENDING the CYCLE_ACTIVITY events have been also added to Sandy Bridge.
> > So it should be also added there.
> >
> As far as I know and I double-checked the documentation I have, there
> is no CYCLE_ACTIVITY
> event on SNB or SNB-EP.

page 19-28 in the Jan 2013 SDM. It was only recently added.
It's only a subset of what you have on Ivy Bridge.

> 
> > In fact I think you can still share the table because it would just add some
> > non existent events to Sandy Bridge, which is a noop.
> >
> I don't see the point of this, except saving a few bytes. Isn't it
> better to keep each PMU separate?

Ok, as long as you update the SNB table too.

-Andi

Re: [PATCH] perf, x86: add Intel IvyBridge event scheduling constraints

[Stephane Eranian]

On Wed, Feb 20, 2013 at 11:08 PM, Andi Kleen <ak@linux.intel.com> wrote:
>> > Except for LDM_PENDING the CYCLE_ACTIVITY events have been also added to Sandy Bridge.
>> > So it should be also added there.
>> >
>> As far as I know and I double-checked the documentation I have, there
>> is no CYCLE_ACTIVITY
>> event on SNB or SNB-EP.
>
> page 19-28 in the Jan 2013 SDM. It was only recently added.
> It's only a subset of what you have on Ivy Bridge.
>
I have confirmed that this is a typo in the SDM. This event is not
available on SandyBridge.

>>
>> > In fact I think you can still share the table because it would just add some
>> > non existent events to Sandy Bridge, which is a noop.
>> >
>> I don't see the point of this, except saving a few bytes. Isn't it
>> better to keep each PMU separate?
>
> Ok, as long as you update the SNB table too.
>
> -Andi

Re: [PATCH] perf, x86: add Intel IvyBridge event scheduling constraints

[yqzhang]

Hi Stephane,

I was wondering what the differences are between
CYCLE_ACTIVITY.CYCLES_**_PENDING and CYCLE_ACTIVITY.STALLS_**_PENDING,
because I could only find following events in the SDM, which seem to be
different from the ones provided here. Correct me if I'm wrong.

A3H 01H CYCLE_ACTIVITY.CYCLES_L2_PENDING
  - Cycles with pending L2 miss loads. Set Cmask=2 tocount cycle. Use only
when HTT is off
A3H 02H CYCLE_ACTIVITY.CYCLES_LDM_PENDING
  - Cycles with pending memory loads. Set Cmask=2 to count cycle.
A3H 05H CYCLE_ACTIVITY.STALLS_L2_PENDING
  - Number of loads missed L2. Use only when HTT is off
A3H 08H CYCLE_ACTIVITY.CYCLES_L1D_PENDING
  - Cycles with pending L1 cache miss loads. SetCmask=8 to count cycle.PMC2
only

Thanks a lot!



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