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From: Dave Jiang <dave.jiang@intel.com>
To: djbw@fb.com
Cc: vinod.koul@intel.com, linux-kernel@vger.kernel.org
Subject: [PATCH 02/10] ioatdma: Add 64bit chansts register read for ioat v3.3.
Date: Tue, 26 Mar 2013 15:42:41 -0700	[thread overview]
Message-ID: <20130326224241.15072.88757.stgit@djiang5-linux2.ch.intel.com> (raw)
In-Reply-To: <20130326223953.15072.26605.stgit@djiang5-linux2.ch.intel.com>

The channel status register for v3.3 is now 64bit. Use readq if available
on v3.3 platforms.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
 drivers/dma/ioat/dma.h |   22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h
index 95ae7b3..9285caa 100644
--- a/drivers/dma/ioat/dma.h
+++ b/drivers/dma/ioat/dma.h
@@ -201,7 +201,7 @@ ioat_chan_by_index(struct ioatdma_device *device, int index)
 	return device->idx[index];
 }
 
-static inline u64 ioat_chansts(struct ioat_chan_common *chan)
+static inline u64 ioat_chansts_32(struct ioat_chan_common *chan)
 {
 	u8 ver = chan->device->version;
 	u64 status;
@@ -218,6 +218,26 @@ static inline u64 ioat_chansts(struct ioat_chan_common *chan)
 	return status;
 }
 
+#if BITS_PER_LONG == 64
+
+static inline u64 ioat_chansts(struct ioat_chan_common *chan)
+{
+	u8 ver = chan->device->version;
+	u64 status;
+
+	 /* With IOAT v3.3 the status register is 64bit.  */
+	if (ver >= IOAT_VER_3_3)
+		status = readq(chan->reg_base + IOAT_CHANSTS_OFFSET(ver));
+	else
+		status = ioat_chansts_32(chan);
+
+	return status;
+}
+
+#else
+#define ioat_chansts ioat_chansts_32
+#endif
+
 static inline void ioat_start(struct ioat_chan_common *chan)
 {
 	u8 ver = chan->device->version;


  parent reply	other threads:[~2013-03-26 22:42 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-03-26 22:42 [PATCH 00/10] Add Intel Atom S1200 seris ioatdma support Dave Jiang
2013-03-26 22:42 ` [PATCH 01/10] ioatdma: Adding PCI IDs for Intel Atom S1200 product family ioatdma devices Dave Jiang
2013-03-26 22:42 ` Dave Jiang [this message]
2013-03-26 22:42 ` [PATCH 03/10] ioatdma: channel reset scheme fixup on Intel Atom S1200 platforms Dave Jiang
2013-03-26 22:42 ` [PATCH 04/10] ioatdma: Removing hw bug workaround for CB3.x .2 and earlier Dave Jiang
2013-03-26 22:42 ` [PATCH 05/10] ioatdma: skip legacy reset bits since v3.3 plattform doesn't need it Dave Jiang
2013-03-26 22:43 ` [PATCH 06/10] ioatdma: Removing PQ val disable for cb3.3 Dave Jiang
2013-03-27 18:48   ` Dan Williams
2013-03-29 17:31     ` Dave Jiang
2013-03-26 22:43 ` [PATCH 07/10] ioatdma: skip silicon bug workaround for pq_align " Dave Jiang
2013-03-26 22:43 ` [PATCH 08/10] ioatdma: Adding support for 16 src PQ ops and super extended descriptors Dave Jiang
2013-03-26 22:43 ` [PATCH 09/10] ioatdma: Adding write back descriptor error status support for ioatdma 3.3 Dave Jiang
2013-03-26 23:47   ` Dan Williams
2013-03-26 23:55     ` Dave Jiang
2013-03-28 22:25     ` [PATCH 09/10 v2] " Jiang, Dave
2013-03-26 22:43 ` [PATCH 10/10] ioatdma: S1200 platforms ioatdma channel 2 and 3 falsely advertise RAID cap Dave Jiang
2013-04-09  7:28 ` [PATCH 00/10] Add Intel Atom S1200 seris ioatdma support Vinod Koul
2013-04-10  0:56   ` Dan Williams
     [not found]   ` <CAA9_cmftcvYN_g0Sj12tMa4T8LxbPdk6wDxwkbTrgQPUUfc0FA@mail.gmail.com>
2013-04-10  5:00     ` Vinod Koul
2013-04-10  5:10       ` Vinod Koul
2013-04-10  5:33       ` Jiang, Dave

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